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authorLey Foon Tan <ley.foon.tan@intel.com>2019-11-27 15:55:27 +0800
committerMarek Vasut <marex@denx.de>2020-01-07 14:38:33 +0100
commit6a48c34c250e41765951586d3389c0df69b2dbe1 (patch)
tree64cb54790f6ee39a919eb7e0d8617fc8b80a2050 /drivers/ddr/altera/sdram_soc64.h
parent733cc6cbcc1c0f212decabceb71925411d1c277c (diff)
ddr: altera: agilex: Add SDRAM driver for Agilex
Add SDRAM driver for Agilex SoC. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'drivers/ddr/altera/sdram_soc64.h')
-rw-r--r--drivers/ddr/altera/sdram_soc64.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
index 7d018e76d81..7b25a80ae26 100644
--- a/drivers/ddr/altera/sdram_soc64.h
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -65,6 +65,7 @@ struct altera_sdram_platdata {
/* HMC MMR IO48 registers */
#define CTRLCFG0 0x28
#define CTRLCFG1 0x2c
+#define CTRLCFG3 0x34
#define DRAMTIMING0 0x50
#define CALTIMING0 0x7c
#define CALTIMING1 0x80