Merge patch series "mediatek: cumulative trivial fix for OF_UPSTREAM support"

Christian Marangi <ansuelsmth@gmail.com> says:

This is an initial series that have all the initial trivial
fixes required for usage of OF_UPSTREAM for the mediatek SoC

This also contains the pcie-gen3 driver and the required tphy
support driver to make it work.

Subsequent series will follow with conversion of the mtk-clk
to permit usage of OF_UPSTREAM and upstream clk ID.

MT7981, MT7986 and MT7988 migration to upstream clock ID
is complete and working on MT7623.

Series CI tested with PR: https://github.com/u-boot/u-boot/pull/590

1 files changed, 19 insertions, 1 deletions

diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c
index 3f569c68f22..becf9317076 100644
--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
@@ -10,6 +10,7 @@
 #include <config.h>
 #include <div64.h>
 #include <dm.h>
+#include <dm/device.h>
 #include <dm/device_compat.h>
 #include <errno.h>
 #include <log.h>
@@ -76,15 +77,19 @@ struct mtk_serial_regs {
  *				driver
  * @regs:			Register base of the serial port
  * @clk:			The baud clock device
+ * @clk_bus:			The bus clock device
  * @fixed_clk_rate:		Fallback fixed baud clock rate if baud clock
  *				device is not specified
  * @force_highspeed:		Force using high-speed mode
+ * @upstream_highspeed_logic:	Apply upstream high-speed logic
  */
 struct mtk_serial_priv {
 	struct mtk_serial_regs __iomem *regs;
 	struct clk clk;
+	struct clk clk_bus;
 	u32 fixed_clk_rate;
 	bool force_highspeed;
+	bool upstream_highspeed_logic;
 };
 
 static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud,
@@ -111,7 +116,12 @@ static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud,
 		goto set_baud;
 	}
 
-	if (priv->force_highspeed)
+	/*
+	 * Upstream linux use highspeed for anything >= 115200 and lowspeed
+	 * for < 115200. Simulate this if we are using the upstream compatible.
+	 */
+	if (priv->force_highspeed ||
+	    (priv->upstream_highspeed_logic && baud >= 115200))
 		goto use_hs3;
 
 	if (baud <= 115200) {
@@ -220,6 +230,10 @@ static int mtk_serial_probe(struct udevice *dev)
 	writel(UART_MCRVAL, &priv->regs->mcr);
 	writel(UART_FCRVAL, &priv->regs->fcr);
 
+	clk_enable(&priv->clk);
+	if (priv->clk_bus.dev)
+		clk_enable(&priv->clk_bus);
+
 	return 0;
 }
 
@@ -250,7 +264,11 @@ static int mtk_serial_of_to_plat(struct udevice *dev)
 		}
 	}
 
+	clk_get_by_name(dev, "bus", &priv->clk_bus);
+
 	priv->force_highspeed = dev_read_bool(dev, "mediatek,force-highspeed");
+	priv->upstream_highspeed_logic =
+		device_is_compatible(dev, "mediatek,mt6577-uart");
 
 	return 0;
 }