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-rw-r--r--arch/arm/Kconfig15
-rw-r--r--arch/arm/Makefile6
-rw-r--r--arch/arm/dts/Makefile10
-rw-r--r--arch/arm/dts/imx6ull.dtsi6
-rw-r--r--arch/arm/dts/imx8mm-ab2-u-boot.dtsi21
-rw-r--r--arch/arm/dts/imx8mm-ab2.dts12
-rw-r--r--arch/arm/dts/imx8mm-ab2.dtsi158
-rw-r--r--arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi21
-rw-r--r--arch/arm/dts/imx8mm-ddr4-ab2.dts12
-rw-r--r--arch/arm/dts/imx8mm-evk.dtsi2
-rw-r--r--arch/arm/dts/imx8mn-ab2-u-boot.dtsi10
-rw-r--r--arch/arm/dts/imx8mn-ab2.dts12
-rw-r--r--arch/arm/dts/imx8mn-ab2.dtsi146
-rw-r--r--arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi18
-rw-r--r--arch/arm/dts/imx8mn-ddr3l-ab2.dts11
-rw-r--r--arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi10
-rw-r--r--arch/arm/dts/imx8mn-ddr4-ab2.dts12
-rw-r--r--arch/arm/dts/imx8mn-evk.dtsi2
-rw-r--r--arch/arm/dts/imx8mp-evk-u-boot.dtsi3
-rw-r--r--arch/arm/dts/imx8mp-evk.dts2
-rw-r--r--arch/arm/dts/imx8mp-sec-def.h3
-rw-r--r--arch/arm/dts/imx8ulp-evk-u-boot.dtsi12
-rw-r--r--arch/arm/dts/imx8ulp-watch-u-boot.dtsi106
-rw-r--r--arch/arm/dts/imx8ulp-watch.dts157
-rw-r--r--arch/arm/dts/imx8ulp.dtsi5
-rw-r--r--arch/arm/dts/imx93-11x11-evk-u-boot.dtsi201
-rw-r--r--arch/arm/dts/imx93-11x11-evk.dts624
-rw-r--r--arch/arm/dts/imx93-pinfunc.h623
-rw-r--r--arch/arm/dts/imx93.dtsi1514
-rw-r--r--arch/arm/dts/ls1021a-twr-u-boot.dtsi29
-rw-r--r--arch/arm/dts/ls1021a-twr.dtsi1
-rw-r--r--arch/arm/include/asm/arch-imx/cpu.h2
-rw-r--r--arch/arm/include/asm/arch-imx8m/ddr.h6
-rw-r--r--arch/arm/include/asm/arch-imx8ulp/imx-regs.h2
-rw-r--r--arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h1
-rw-r--r--arch/arm/include/asm/arch-imx8ulp/s400_api.h46
-rw-r--r--arch/arm/include/asm/arch-imx8ulp/sys_proto.h1
-rw-r--r--arch/arm/include/asm/arch-imx9/ccm_regs.h266
-rw-r--r--arch/arm/include/asm/arch-imx9/clock.h249
-rw-r--r--arch/arm/include/asm/arch-imx9/ddr.h128
-rw-r--r--arch/arm/include/asm/arch-imx9/gpio.h22
-rw-r--r--arch/arm/include/asm/arch-imx9/imx-regs.h246
-rw-r--r--arch/arm/include/asm/arch-imx9/imx93_pins.h729
-rw-r--r--arch/arm/include/asm/arch-imx9/sys_proto.h20
-rw-r--r--arch/arm/include/asm/arch-imx9/trdc.h21
-rw-r--r--arch/arm/include/asm/global_data.h8
-rw-r--r--arch/arm/include/asm/mach-imx/iomux-v3.h11
-rw-r--r--arch/arm/include/asm/mach-imx/mu_hal.h (renamed from arch/arm/include/asm/arch-imx8ulp/mu_hal.h)4
-rw-r--r--arch/arm/include/asm/mach-imx/s400_api.h148
-rw-r--r--arch/arm/include/asm/mach-imx/sys_proto.h12
-rw-r--r--arch/arm/mach-imx/Kconfig2
-rw-r--r--arch/arm/mach-imx/Makefile11
-rw-r--r--arch/arm/mach-imx/ele_ahab.c590
-rw-r--r--arch/arm/mach-imx/image-container.c58
-rw-r--r--arch/arm/mach-imx/imx8m/Kconfig46
-rw-r--r--arch/arm/mach-imx/imx8ulp/Kconfig12
-rw-r--r--arch/arm/mach-imx/imx8ulp/Makefile1
-rw-r--r--arch/arm/mach-imx/imx8ulp/ahab.c349
-rw-r--r--arch/arm/mach-imx/imx8ulp/cgc.c3
-rw-r--r--arch/arm/mach-imx/imx8ulp/clock.c5
-rw-r--r--arch/arm/mach-imx/imx8ulp/rdc.c38
-rw-r--r--arch/arm/mach-imx/imx8ulp/soc.c196
-rw-r--r--arch/arm/mach-imx/imx8ulp/upower/upower_hal.c27
-rw-r--r--arch/arm/mach-imx/imx9/Kconfig35
-rw-r--r--arch/arm/mach-imx/imx9/Makefile10
-rw-r--r--arch/arm/mach-imx/imx9/clock.c882
-rw-r--r--arch/arm/mach-imx/imx9/clock_root.c450
-rw-r--r--arch/arm/mach-imx/imx9/imx_bootaux.c138
-rw-r--r--arch/arm/mach-imx/imx9/lowlevel_init.S26
-rw-r--r--arch/arm/mach-imx/imx9/soc.c614
-rw-r--r--arch/arm/mach-imx/imx9/trdc.c593
-rw-r--r--arch/arm/mach-imx/mx6/soc.c16
-rw-r--r--arch/arm/mach-imx/spl.c2
-rw-r--r--arch/arm/mach-imx/spl_imx_romapi.c23
-rw-r--r--board/freescale/common/Kconfig1
-rw-r--r--board/freescale/common/Makefile2
-rw-r--r--board/freescale/common/fsl_chain_of_trust.c6
-rw-r--r--board/freescale/common/fsl_validate.c10
-rw-r--r--board/freescale/common/tcpc.c30
-rw-r--r--board/freescale/imx8dxl_evk/spl.c4
-rw-r--r--board/freescale/imx8mm_ab2/Kconfig29
-rw-r--r--board/freescale/imx8mm_ab2/MAINTAINERS8
-rw-r--r--board/freescale/imx8mm_ab2/Makefile21
-rw-r--r--board/freescale/imx8mm_ab2/ddr3l_imx8mn_som.c944
-rw-r--r--board/freescale/imx8mm_ab2/ddr4_imx8mm_som.c1265
-rw-r--r--board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c1057
-rw-r--r--board/freescale/imx8mm_ab2/ddr4_imx8mn_som_ld.c1056
-rw-r--r--board/freescale/imx8mm_ab2/imx8mm_ab2.c234
-rw-r--r--board/freescale/imx8mm_ab2/imximage-8mm-fspi.cfg7
-rw-r--r--board/freescale/imx8mm_ab2/imximage-8mm.cfg8
-rw-r--r--board/freescale/imx8mm_ab2/imximage-8mn.cfg9
-rw-r--r--board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c1855
-rw-r--r--board/freescale/imx8mm_ab2/lpddr4_imx8mn_som.c1585
-rw-r--r--board/freescale/imx8mm_ab2/lpddr4_imx8mn_som_ld.c1440
-rw-r--r--board/freescale/imx8mm_ab2/spl.c473
-rw-r--r--board/freescale/imx8mm_evk/imx8mm_evk.c18
-rw-r--r--board/freescale/imx8mn_evk/imx8mn_evk.c18
-rw-r--r--board/freescale/imx8mp_evk/imx8mp_evk.c18
-rw-r--r--board/freescale/imx8mq_evk/imx8mq_evk.c18
-rw-r--r--board/freescale/imx8mq_evk/lpddr4_timing.c15
-rw-r--r--board/freescale/imx8mq_evk/spl.c6
-rw-r--r--board/freescale/imx8ulp_evk/imx8ulp_evk.c8
-rw-r--r--board/freescale/imx8ulp_evk/lpddr4_timing.c4
-rw-r--r--board/freescale/imx8ulp_evk/lpddr4_timing_266.c4
-rw-r--r--board/freescale/imx8ulp_evk/lpddr4_timing_9x9.c4
-rw-r--r--board/freescale/imx8ulp_evk/spl.c21
-rw-r--r--board/freescale/imx8ulp_watch/Kconfig14
-rw-r--r--board/freescale/imx8ulp_watch/MAINTAINERS6
-rw-r--r--board/freescale/imx8ulp_watch/Makefile8
-rw-r--r--board/freescale/imx8ulp_watch/imx8ulp_watch.c130
-rw-r--r--board/freescale/imx8ulp_watch/lpddr4x_timing.c1159
-rw-r--r--board/freescale/imx8ulp_watch/spl.c205
-rw-r--r--board/freescale/imx93_evk/Kconfig21
-rw-r--r--board/freescale/imx93_evk/Makefile12
-rw-r--r--board/freescale/imx93_evk/imx93_evk.c286
-rw-r--r--board/freescale/imx93_evk/lpddr4x_timing.c1488
-rw-r--r--board/freescale/imx93_evk/spl.c130
-rw-r--r--board/freescale/ls1021aiot/ls1021aiot.c10
-rw-r--r--board/freescale/ls1021aqds/eth.c5
-rw-r--r--board/freescale/ls1021atwr/ls1021atwr.c13
-rw-r--r--board/freescale/ls1043ardb/cpld.c6
-rw-r--r--board/freescale/ls1043ardb/cpld.h1
-rw-r--r--board/freescale/ls1043ardb/ls1043ardb.c79
-rw-r--r--board/freescale/mx7ulp_evk/mx7ulp_evk.c1
-rw-r--r--common/spl/Kconfig1
-rw-r--r--configs/imx8mm_ab2_defconfig194
-rw-r--r--configs/imx8mm_ddr4_ab2_defconfig163
-rw-r--r--configs/imx8mm_evk_android_trusty_secure_unlock_dual_defconfig (renamed from configs/imx8mm_evk_android_trusty_secure_unlock_defconfig)1
-rw-r--r--configs/imx8mn_ab2_defconfig159
-rw-r--r--configs/imx8mn_ddr3l_ab2_defconfig141
-rw-r--r--configs/imx8mn_ddr4_ab2_defconfig154
-rw-r--r--configs/imx8mn_evk_android_trusty_secure_unlock_dual_defconfig (renamed from configs/imx8mn_evk_android_trusty_secure_unlock_defconfig)1
-rw-r--r--configs/imx8mp_evk_android_trusty_powersave_dual_defconfig (renamed from configs/imx8mp_evk_android_trusty_powersave_defconfig)2
-rw-r--r--configs/imx8mp_evk_android_trusty_secure_unlock_dual_defconfig (renamed from configs/imx8mp_evk_android_trusty_secure_unlock_defconfig)1
-rw-r--r--configs/imx8mq_evk_android_trusty_secure_unlock_dual_defconfig (renamed from configs/imx8mq_evk_android_trusty_secure_unlock_defconfig)1
-rw-r--r--configs/imx8qm_mek_android_trusty_secure_unlock_dual_defconfig (renamed from configs/imx8qm_mek_android_trusty_secure_unlock_defconfig)1
-rw-r--r--configs/imx8qxp_mek_android_trusty_secure_unlock_dual_defconfig (renamed from configs/imx8qxp_mek_android_trusty_secure_unlock_defconfig)1
-rw-r--r--configs/imx8ulp_9x9_evk_android_defconfig2
-rw-r--r--configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig (renamed from configs/imx8ulp_9x9_evk_android_trusty_defconfig)3
-rw-r--r--configs/imx8ulp_9x9_evk_android_uuu_defconfig2
-rw-r--r--configs/imx8ulp_9x9_evk_defconfig2
-rw-r--r--configs/imx8ulp_9x9_evk_i3c_defconfig2
-rw-r--r--configs/imx8ulp_evk_android_defconfig2
-rw-r--r--configs/imx8ulp_evk_android_dual_defconfig2
-rw-r--r--configs/imx8ulp_evk_android_trusty_defconfig2
-rw-r--r--configs/imx8ulp_evk_android_trusty_dual_defconfig2
-rw-r--r--configs/imx8ulp_evk_android_trusty_secure_unlock_dual_defconfig (renamed from configs/imx8ulp_evk_android_trusty_secure_unlock_defconfig)3
-rw-r--r--configs/imx8ulp_evk_android_uuu_defconfig2
-rw-r--r--configs/imx8ulp_evk_defconfig2
-rw-r--r--configs/imx8ulp_evk_i3c_defconfig2
-rw-r--r--configs/imx8ulp_evk_nd_defconfig2
-rw-r--r--configs/imx8ulp_watch_android_defconfig138
-rw-r--r--configs/imx8ulp_watch_android_dual_defconfig139
-rw-r--r--configs/imx8ulp_watch_android_trusty_dual_defconfig145
-rw-r--r--configs/imx8ulp_watch_android_uuu_defconfig133
-rw-r--r--configs/imx93_11x11_evk_defconfig172
-rw-r--r--configs/ls1043ardb_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1043ardb_defconfig1
-rw-r--r--configs/ls1043ardb_nand_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1043ardb_nand_defconfig1
-rw-r--r--configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1043ardb_sdcard_defconfig1
-rw-r--r--configs/ls1043ardb_tfa_SECURE_BOOT_defconfig1
-rw-r--r--configs/ls1043ardb_tfa_defconfig5
-rw-r--r--configs/mx6ull_14x14_evk_defconfig4
-rw-r--r--configs/mx6ull_14x14_evk_emmc_defconfig4
-rw-r--r--configs/mx6ull_14x14_evk_nand_defconfig4
-rw-r--r--configs/mx6ull_14x14_evk_optee_defconfig4
-rw-r--r--configs/mx6ull_14x14_evk_plugin_defconfig4
-rw-r--r--configs/mx6ull_14x14_evk_qspi1_defconfig4
-rw-r--r--configs/mx6ull_9x9_evk_defconfig5
-rw-r--r--configs/mx6ull_9x9_evk_plugin_defconfig4
-rw-r--r--configs/mx6ull_9x9_evk_qspi1_defconfig4
-rw-r--r--configs/sandbox64_defconfig1
-rw-r--r--configs/sandbox_defconfig1
-rw-r--r--configs/sandbox_flattree_defconfig5
-rw-r--r--doc/develop/uefi/uefi.rst100
-rw-r--r--doc/mkeficapsule.112
-rw-r--r--drivers/Makefile1
-rw-r--r--drivers/clk/clk.c18
-rw-r--r--drivers/clk/imx/Kconfig20
-rw-r--r--drivers/clk/imx/Makefile1
-rw-r--r--drivers/clk/imx/clk-fracn-gppll.c244
-rw-r--r--drivers/clk/imx/clk-imx93.c430
-rw-r--r--drivers/clk/imx/clk.h12
-rw-r--r--drivers/cpu/imx8_cpu.c7
-rw-r--r--drivers/crypto/fsl/Kconfig10
-rw-r--r--drivers/crypto/fsl/Makefile1
-rw-r--r--drivers/crypto/fsl/dcp_rng.c184
-rw-r--r--drivers/crypto/fsl/fsl_hash.c10
-rw-r--r--drivers/crypto/fsl/fsl_rsa.c5
-rw-r--r--drivers/ddr/imx/Kconfig2
-rw-r--r--drivers/ddr/imx/imx8m/Kconfig1
-rw-r--r--drivers/ddr/imx/imx8m/Makefile3
-rw-r--r--drivers/ddr/imx/imx8m/ddr_init.c213
-rw-r--r--drivers/ddr/imx/imx8m/ddrphy_utils.c360
-rw-r--r--drivers/ddr/imx/imx8ulp/Kconfig2
-rw-r--r--drivers/ddr/imx/imx9/Kconfig27
-rw-r--r--drivers/ddr/imx/imx9/Makefile10
-rw-r--r--drivers/ddr/imx/imx9/ddr_init.c386
-rw-r--r--drivers/ddr/imx/phy/Kconfig4
-rw-r--r--drivers/ddr/imx/phy/Makefile9
-rw-r--r--drivers/ddr/imx/phy/ddrphy_csr.c (renamed from drivers/ddr/imx/imx8m/ddrphy_csr.c)0
-rw-r--r--drivers/ddr/imx/phy/ddrphy_train.c (renamed from drivers/ddr/imx/imx8m/ddrphy_train.c)1
-rw-r--r--drivers/ddr/imx/phy/ddrphy_utils.c169
-rw-r--r--drivers/ddr/imx/phy/helper.c (renamed from drivers/ddr/imx/imx8m/helper.c)41
-rw-r--r--drivers/fastboot/fb_fsl/fb_fsl_common.c3
-rw-r--r--drivers/fastboot/fb_fsl/fb_fsl_partitions.c2
-rw-r--r--drivers/firmware/scmi/scmi_agent-uclass.c4
-rw-r--r--drivers/gpio/Kconfig6
-rw-r--r--drivers/gpio/Makefile5
-rw-r--r--drivers/gpio/adp5585_gpio.c238
-rw-r--r--drivers/gpio/pca953x_gpio.c4
-rw-r--r--drivers/i2c/imx_lpi2c.c4
-rw-r--r--drivers/misc/Kconfig7
-rw-r--r--drivers/misc/Makefile2
-rw-r--r--drivers/misc/sentinel/Makefile (renamed from drivers/misc/imx8ulp/Makefile)2
-rw-r--r--drivers/misc/sentinel/fuse.c (renamed from drivers/misc/imx8ulp/fuse.c)96
-rw-r--r--drivers/misc/sentinel/s400_api.c (renamed from drivers/misc/imx8ulp/s400_api.c)239
-rw-r--r--drivers/misc/sentinel/s4mu.c (renamed from drivers/misc/imx8ulp/imx8ulp_mu.c)15
-rw-r--r--drivers/mmc/Kconfig2
-rw-r--r--drivers/mmc/mmc.c5
-rw-r--r--drivers/net/Kconfig2
-rw-r--r--drivers/net/dwc_eth_qos.c17
-rw-r--r--drivers/net/fec_mxc.c4
-rw-r--r--drivers/net/pfe_eth/pfe_firmware.c2
-rw-r--r--drivers/net/phy/realtek.c15
-rw-r--r--drivers/phy/Kconfig9
-rw-r--r--drivers/phy/Makefile1
-rw-r--r--drivers/phy/phy-imx93-mipi-dphy.c527
-rw-r--r--drivers/pinctrl/nxp/Kconfig13
-rw-r--r--drivers/pinctrl/nxp/Makefile1
-rw-r--r--drivers/pinctrl/nxp/pinctrl-imx8m.c5
-rw-r--r--drivers/power/domain/Kconfig6
-rw-r--r--drivers/power/domain/Makefile1
-rw-r--r--drivers/power/domain/imx93-blk-ctrl.c259
-rw-r--r--drivers/power/domain/power-domain-uclass.c9
-rw-r--r--drivers/power/pmic/pca9450.c1
-rw-r--r--drivers/serial/serial_lpuart.c4
-rw-r--r--drivers/thermal/Kconfig6
-rw-r--r--drivers/thermal/Makefile1
-rw-r--r--drivers/thermal/scmi_thermal.c176
-rw-r--r--drivers/usb/gadget/ci_udc.c6
-rw-r--r--drivers/usb/host/Kconfig6
-rw-r--r--drivers/usb/host/ehci-mx6.c2
-rw-r--r--drivers/video/Kconfig9
-rw-r--r--drivers/video/Makefile1
-rw-r--r--drivers/video/adv7535.c2
-rw-r--r--drivers/video/bridge/video-bridge-uclass.c10
-rw-r--r--drivers/video/dw_mipi_dsi.c37
-rw-r--r--drivers/video/nxp/imx/Kconfig11
-rw-r--r--drivers/video/nxp/imx/Makefile1
-rw-r--r--drivers/video/nxp/imx/dw_dsi_imx.c436
-rw-r--r--drivers/video/nxp/imx/imx_lcdifv3.c7
-rw-r--r--drivers/video/raydium-rm67191.c2
-rw-r--r--drivers/video/usmp-rm67162.c461
-rw-r--r--drivers/watchdog/ulp_wdog.c12
-rw-r--r--fs/fat/fat_write.c19
-rw-r--r--include/configs/imx8mm_ab2.h303
-rw-r--r--include/configs/imx8mm_evk.h5
-rw-r--r--include/configs/imx8mn_ab2.h270
-rw-r--r--include/configs/imx8mn_evk.h5
-rw-r--r--include/configs/imx8mp_evk.h5
-rw-r--r--include/configs/imx8mq_evk.h5
-rw-r--r--include/configs/imx8ulp_watch.h202
-rw-r--r--include/configs/imx93_evk.h212
-rw-r--r--include/configs/imx_env.h24
-rw-r--r--include/configs/ls1043ardb.h5
-rw-r--r--include/dt-bindings/clock/imx93-clock.h203
-rw-r--r--include/dt-bindings/power/imx93-power.h18
-rw-r--r--include/efi_api.h8
-rw-r--r--include/efi_loader.h36
-rw-r--r--include/fsl_lpuart.h2
-rw-r--r--include/imx_sip.h1
-rw-r--r--include/net.h2
-rw-r--r--include/scmi_protocols.h90
-rw-r--r--include/video_bridge.h20
-rwxr-xr-xlib/avb/fsl/fsl_bootctrl.c26
-rw-r--r--lib/efi_loader/Kconfig2
-rw-r--r--lib/efi_loader/efi_capsule.c8
-rw-r--r--lib/efi_loader/efi_firmware.c107
-rw-r--r--lib/trusty/ql-tipc/arch/arm/trusty_mem.c2
-rw-r--r--lib/trusty/ql-tipc/keymaster.c17
-rw-r--r--lib/trusty/ql-tipc/rpmb_proxy.c2
-rw-r--r--lib/trusty/ql-tipc/sysdeps/storage_ops_uboot.c6
-rw-r--r--net/net.c3
-rw-r--r--test/py/tests/test_efi_capsule/conftest.py21
-rw-r--r--test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py191
-rw-r--r--test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py (renamed from test/py/tests/test_efi_capsule/test_capsule_firmware.py)167
-rw-r--r--tools/eficapsule.h8
-rw-r--r--tools/mkeficapsule.c26
291 files changed, 30817 insertions, 1381 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3284211556..c65cad54a6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -839,6 +839,19 @@ config ARCH_IMX8ULP
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_LE
select SYS_FSL_SEC_COMPAT_4
+ select MISC
+ select IMX_SENTINEL
+ imply CMD_DM
+
+config ARCH_IMX9
+ bool "NXP i.MX9 platform"
+ select ARM64
+ select DM
+ select MACH_IMX
+ select SUPPORT_SPL
+ select GPIO_EXTRA_HEADER
+ select MISC
+ select IMX_SENTINEL
imply CMD_DM
config ARCH_IMXRT
@@ -2137,6 +2150,8 @@ source "arch/arm/mach-imx/imx8m/Kconfig"
source "arch/arm/mach-imx/imx8ulp/Kconfig"
+source "arch/arm/mach-imx/imx9/Kconfig"
+
source "arch/arm/mach-imx/imxrt/Kconfig"
source "arch/arm/mach-imx/mxs/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index f35b246a5c..5bfc30861b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -32,7 +32,7 @@ else
arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
endif
-ifneq ($(CONFIG_ARCH_IMX8)$(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8ULP),)
+ifneq ($(CONFIG_ARCH_IMX8)$(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8ULP)$(CONFIG_ARCH_IMX9),)
arch-y += -mgeneral-regs-only
endif
@@ -116,11 +116,11 @@ libs-y += arch/arm/cpu/
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imx9 imxrt))
libs-y += arch/arm/mach-imx/
endif
else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imx8ulp imxrt vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imx8ulp imx9 imxrt vf610))
libs-y += arch/arm/mach-imx/
endif
endif
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8d35a96f61..f27ff45770 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -959,13 +959,16 @@ dtb-$(CONFIG_ARCH_IMX8ULP) += \
imx8ulp-evk.dtb \
imx8ulp-evk-i3c.dtb \
imx8ulp-9x9-evk.dtb \
- imx8ulp-9x9-evk-i3c.dtb
+ imx8ulp-9x9-evk-i3c.dtb \
+ imx8ulp-watch.dtb
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-ddr4-evk.dtb \
+ imx8mm-ddr4-ab2.dtb \
imx8mm-ddr3l-val.dtb \
imx8mm-ddr4-val.dtb \
imx8mm-evk.dtb \
+ imx8mm-ab2.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
imx8mm-icore-mx8mm-edimm2.2.dtb \
imx8mm-kontron-n801x-s.dtb \
@@ -980,8 +983,10 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
phycore-imx8mm.dtb \
imx8mn-ddr3l-evk.dtb \
imx8mn-ddr4-evk.dtb \
+ imx8mn-ddr4-ab2.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
+ imx8mn-ab2.dtb \
imx8mn-var-som-symphony.dtb \
imx8mn-venice.dtb \
imx8mn-venice-gw7902.dtb \
@@ -999,6 +1004,9 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-pico-pi.dtb \
imx8mq-kontron-pitx-imx8m.dtb
+dtb-$(CONFIG_ARCH_IMX9) += \
+ imx93-11x11-evk.dtb
+
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb
diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi
index 46e7ad6bab..c5d5a5ab7b 100644
--- a/arch/arm/dts/imx6ull.dtsi
+++ b/arch/arm/dts/imx6ull.dtsi
@@ -66,6 +66,12 @@
clocks = <&clks IMX6ULL_CLK_DCP_CLK>;
clock-names = "dcp";
};
+ rngb: rng@2284000 {
+ compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb";
+ reg = <0x02284000 0x4000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_DUMMY>;
+ };
iomuxc_snvs: iomuxc-snvs@2290000 {
compatible = "fsl,imx6ull-iomuxc-snvs";
diff --git a/arch/arm/dts/imx8mm-ab2-u-boot.dtsi b/arch/arm/dts/imx8mm-ab2-u-boot.dtsi
new file mode 100644
index 0000000000..c0b93bf9c1
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ab2-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mm-evk-u-boot.dtsi"
+
+/ {
+ usbg2: usbg2 {
+ status = "disabled";
+ };
+};
+
+&fec1 {
+ phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+};
+
+&usbotg1 {
+ status = "okay";
+ extcon = <&ptn5150>;
+};
diff --git a/arch/arm/dts/imx8mm-ab2.dts b/arch/arm/dts/imx8mm-ab2.dts
new file mode 100644
index 0000000000..6d3667ef9a
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ab2.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mm-evk.dts"
+#include "imx8mm-ab2.dtsi"
+
+/ {
+ model = "NXP i.MX8MM Audio board 2.0";
+ compatible = "fsl,imx8mm-ab2", "fsl,imx8mm";
+};
diff --git a/arch/arm/dts/imx8mm-ab2.dtsi b/arch/arm/dts/imx8mm-ab2.dtsi
new file mode 100644
index 0000000000..d945d27c54
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ab2.dtsi
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 NXP
+ */
+
+/ {
+ /delete-node/ audio-codec;
+ /delete-node/ dsi-host;
+ /delete-node/ ir-receiver;
+ /delete-node/ rm67199_panel;
+ /delete-node/ sound-wm8524;
+
+ leds {
+ panel {
+ label = "green:panel";
+ gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+ };
+
+ reg_ab2_ana_pwr: regulator-ab2-ana-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "ANA_12V0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ab2_ana_pwr>;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&buck5_reg>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_5V0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&buck5_reg>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&fec1 {
+ mdio {
+ ethphy0: ethernet-phy@0 {
+ reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ max-speed = <100>;
+ };
+ };
+};
+
+&i2c2 {
+ /delete-node/ adv7535@3d;
+ /delete-node/ tcpc@50;
+
+ pca6408_2: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ ptn5150: tcpc@1d {
+ compatible = "nxp,ptn5150";
+ reg = <0x1d>;
+ status = "okay";
+
+ port {
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+
+ typec1_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ op-sink-microwatt = <15000000>;
+ self-powered;
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ENET_PHY_RST_B */
+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* ENET_PHY_INT_B */
+ >;
+ };
+
+ pinctrl_ab2_ana_pwr: ab2anapwrgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
+ >;
+ };
+
+ pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ >;
+ };
+};
+
+&lcdif {
+ status = "disabled";
+};
+
+&mipi_dsi {
+ status = "disabled";
+
+ /delete-node/ port@1;
+ /delete-node/ port@2;
+};
+
+&sai3 {
+ status = "disabled";
+};
+
+&usbotg1 {
+ extcon = <&ptn5150>;
+};
+
+&usdhc2 {
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi b/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi
new file mode 100644
index 0000000000..27daf58a22
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mm-ddr4-evk-u-boot.dtsi"
+
+/ {
+ usbg2: usbg2 {
+ status = "disabled";
+ };
+};
+
+&fec1 {
+ phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+};
+
+&usbotg1 {
+ status = "okay";
+ extcon = <&ptn5150>;
+};
diff --git a/arch/arm/dts/imx8mm-ddr4-ab2.dts b/arch/arm/dts/imx8mm-ddr4-ab2.dts
new file mode 100644
index 0000000000..418db5789e
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ddr4-ab2.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mm-ddr4-evk.dts"
+#include "imx8mm-ab2.dtsi"
+
+/ {
+ model = "NXP i.MX8MM DDR4 Audio board 2.0";
+ compatible = "fsl,imx8mm-ab2", "fsl,imx8mm";
+};
diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
index 9d8f07cfa9..95d339bb37 100644
--- a/arch/arm/dts/imx8mm-evk.dtsi
+++ b/arch/arm/dts/imx8mm-evk.dtsi
@@ -300,7 +300,7 @@
status = "okay";
adv_bridge: adv7535@3d {
- compatible = "adi,adv7533";
+ compatible = "adi,adv7535";
reg = <0x3d>;
adi,addr-cec = <0x3c>;
adi,dsi-lanes = <4>;
diff --git a/arch/arm/dts/imx8mn-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ab2-u-boot.dtsi
new file mode 100644
index 0000000000..689f6f3218
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ab2-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mn-evk-u-boot.dtsi"
+
+&fec1 {
+ phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/imx8mn-ab2.dts b/arch/arm/dts/imx8mn-ab2.dts
new file mode 100644
index 0000000000..9a5b5f63f8
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ab2.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mn-evk.dts"
+#include "imx8mn-ab2.dtsi"
+
+/ {
+ model = "NXP i.MX8MNano LPDDR4 Audio board 2.0";
+ compatible = "fsl,imx8mn-ab2", "fsl,imx8mn";
+};
diff --git a/arch/arm/dts/imx8mn-ab2.dtsi b/arch/arm/dts/imx8mn-ab2.dtsi
new file mode 100644
index 0000000000..039f3d549a
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ab2.dtsi
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+/ {
+ /delete-node/ dsi-host;
+ /delete-node/ ir-receiver;
+ /delete-node/ rm67199_panel;
+
+ gpio-leds {
+ panel {
+ label = "green:panel";
+ gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+ };
+
+ reg_ab2_ana_pwr: regulator-ab2-ana-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "ANA_12V0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ab2_ana_pwr>;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ };
+};
+
+&fec1 {
+ phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+
+ mdio {
+ ethphy0: ethernet-phy@0 {
+ max-speed = <100>;
+ };
+ };
+};
+
+&i2c2 {
+ /delete-node/ adv7535@3d;
+ /delete-node/ tcpc@50;
+
+ pca6408_2: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ ptn5150: tcpc@1d {
+ compatible = "nxp,ptn5150";
+ reg = <0x1d>;
+ status = "okay";
+
+ port {
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+
+ typec1_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ op-sink-microwatt = <15000000>;
+ self-powered;
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16
+ >;
+ };
+
+ pinctrl_ab2_ana_pwr: ab2anapwrgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
+ >;
+ };
+
+ pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ >;
+ };
+};
+
+&lcdif {
+ status = "disabled";
+};
+
+&mipi_dsi {
+ status = "disabled";
+
+ /delete-node/ port@1;
+ /delete-node/ port@2;
+};
+
+&usdhc2 {
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+};
+
+&usbotg1 {
+ extcon = <&ptn5150>;
+};
diff --git a/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi
new file mode 100644
index 0000000000..9d595da3a9
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mn-ab2-u-boot.dtsi"
+
+&blob_1 {
+ filename = "ddr3_imem_1d_201810.bin";
+};
+
+&blob_2 {
+ filename = "ddr3_dmem_1d_201810.bin";
+};
+
+/delete-node/ &blob_3;
+
+/delete-node/ &blob_4;
diff --git a/arch/arm/dts/imx8mn-ddr3l-ab2.dts b/arch/arm/dts/imx8mn-ddr3l-ab2.dts
new file mode 100644
index 0000000000..b89e1ce81b
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr3l-ab2.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+ /*
+ * Copyright 2021 NXP
+ */
+
+#include "imx8mn-ddr3l-evk.dts"
+#include "imx8mn-ab2.dtsi"
+
+/ {
+ model = "NXP i.MX8MNano DDR3L Audio board 2.0";
+};
diff --git a/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi
new file mode 100644
index 0000000000..6df56985d6
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mn-ddr4-evk-u-boot.dtsi"
+
+&fec1 {
+ phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/imx8mn-ddr4-ab2.dts b/arch/arm/dts/imx8mn-ddr4-ab2.dts
new file mode 100644
index 0000000000..40c9c56bfc
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr4-ab2.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mn-ddr4-evk.dts"
+#include "imx8mn-ab2.dtsi"
+
+/ {
+ model = "NXP i.MX8MNano DDR4 Audio board 2.0";
+ compatible = "fsl,imx8mn-ab2", "fsl,imx8mn";
+};
diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi
index 00c91d1ae4..d533520efa 100644
--- a/arch/arm/dts/imx8mn-evk.dtsi
+++ b/arch/arm/dts/imx8mn-evk.dtsi
@@ -115,7 +115,7 @@
status = "okay";
adv_bridge: adv7535@3d {
- compatible = "adi,adv7533";
+ compatible = "adi,adv7535";
reg = <0x3d>;
adi,addr-cec = <0x3c>;
adi,dsi-lanes = <4>;
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index 16d98cb659..203d05e66e 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -39,8 +39,11 @@
*/
start-config = <
RDC_MDA RDC_MDA_SDMA3p DID1 0x0 0x0
+ RDC_MDA RDC_MDA_ENET1_TX DID1 0x0 0x0
+ RDC_MDA RDC_MDA_ENET1_RX DID1 0x0 0x0
RDC_MDA RDC_MDA_SDMA3b DID1 0x0 0x0
RDC_MDA RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0
+ RDC_PDAP RDC_PDAP_ENET1 PDAP_D0D1_ACCESS 0x0 0x0
RDC_PDAP RDC_PDAP_SAI3 PDAP_D1_ACCESS 0x0 0x0
RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0
RDC_PDAP RDC_PDAP_GPT1 PDAP_D1_ACCESS 0x0 0x0
diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts
index a5c797d357..0df546dfd0 100644
--- a/arch/arm/dts/imx8mp-evk.dts
+++ b/arch/arm/dts/imx8mp-evk.dts
@@ -308,7 +308,7 @@
status = "okay";
adv_bridge: adv7535@3d {
- compatible = "adi,adv7533";
+ compatible = "adi,adv7535";
reg = <0x3d>;
adi,addr-cec = <0x3c>;
adi,dsi-lanes = <4>;
diff --git a/arch/arm/dts/imx8mp-sec-def.h b/arch/arm/dts/imx8mp-sec-def.h
index 420e584bff..155aab1428 100644
--- a/arch/arm/dts/imx8mp-sec-def.h
+++ b/arch/arm/dts/imx8mp-sec-def.h
@@ -26,6 +26,7 @@
#define D0W 0x00000001
#define PDAP_D1_ACCESS 0x0000000C /* D1W|D1R */
+#define PDAP_D0D1_ACCESS 0x0000000F /* D0R|D0W|D1W|D1R */
#define MEM_D1_ACCESS 0x4000000C /* ENA|D1W|D1R */
#define MEM_D0D1_ACCESS 0x4000000F /* ENA|D0W|D0R|D1W|D1R */
@@ -53,6 +54,8 @@
#define RDC_MDA_uSDHC1 15
#define RDC_MDA_uSDHC2 16
#define RDC_MDA_uSDHC3 17
+#define RDC_MDA_ENET1_TX 22
+#define RDC_MDA_ENET1_RX 23
#define RDC_MDA_SDMA3_SPBA2 25
#define RDC_MDA_LCDIF2 27
#define RDC_MDA_HDMI_TX 28
diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
index 0c2dcc0792..b22d62c0d9 100644
--- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
@@ -33,6 +33,18 @@
u-boot,dm-spl;
};
+&{/firmware} {
+ u-boot,dm-pre-reloc;
+};
+
+&{/firmware/scmi} {
+ u-boot,dm-pre-reloc;
+};
+
+&{/firmware/scmi/protocol@15} {
+ u-boot,dm-pre-reloc;
+};
+
&per_bridge3 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8ulp-watch-u-boot.dtsi b/arch/arm/dts/imx8ulp-watch-u-boot.dtsi
new file mode 100644
index 0000000000..a918ce0a05
--- /dev/null
+++ b/arch/arm/dts/imx8ulp-watch-u-boot.dtsi
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+/ {
+ aliases {
+ usbgadget0 = &usbg1;
+ };
+
+ usbg1: usbg1 {
+ compatible = "fsl,imx27-usb-gadget";
+ dr_mode = "peripheral";
+ chipidea,usb = <&usbotg1>;
+ status = "okay";
+ };
+
+ dsi_host: dsi-host {
+ compatible = "northwest,mipi-dsi";
+ status = "okay";
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-spl;
+};
+
+&{/firmware} {
+ u-boot,dm-pre-reloc;
+};
+
+&{/firmware/scmi} {
+ u-boot,dm-pre-reloc;
+};
+
+&{/firmware/scmi/protocol@15} {
+ u-boot,dm-pre-reloc;
+};
+
+&per_bridge3 {
+ u-boot,dm-spl;
+};
+
+&per_bridge4 {
+ u-boot,dm-spl;
+};
+
+&iomuxc1 {
+ u-boot,dm-spl;
+ fsl,mux_mask = <0xf00>;
+};
+
+&pinctrl_lpuart5 {
+ u-boot,dm-spl;
+};
+
+&s400_mu {
+ u-boot,dm-spl;
+};
+
+&lpuart5 {
+ u-boot,dm-spl;
+};
+
+&usdhc0 {
+ u-boot,dm-spl;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+};
+
+&pinctrl_usdhc0 {
+ u-boot,dm-spl;
+};
+
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
+&sec_jr3 {
+ u-boot,dm-spl;
+};
+
+&scmi_buf {
+ reg = <0x0 0x1000>; /* Align page size */
+};
+
+&dsi {
+ data-lanes-num = <4>;
+};
+
+&usbotg1 {
+ compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx27-usb";
+ fsl,usbphy = <&usbphy1>;
+};
diff --git a/arch/arm/dts/imx8ulp-watch.dts b/arch/arm/dts/imx8ulp-watch.dts
new file mode 100644
index 0000000000..232485486c
--- /dev/null
+++ b/arch/arm/dts/imx8ulp-watch.dts
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2022 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8ulp.dtsi"
+
+/ {
+ model = "NXP i.MX8ULP WATCH";
+ compatible = "fsl,imx8ulp-watch", "fsl,imx8ulp";
+
+ chosen {
+ stdout-path = &lpuart5;
+ bootargs = "console=ttyLP1,115200 earlycon";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x28000000>;
+ linux,cma-default;
+ };
+
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+
+&clock_ext_ts {
+ /* External ts clock is 50MHZ from PHY on EVK board. */
+ clock-frequency = <50000000>;
+};
+
+&lpuart5 {
+ /* console */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpuart5>;
+ pinctrl-1 = <&pinctrl_lpuart5>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_otgid1>;
+ pinctrl-1 = <&pinctrl_otgid1>;
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ over-current-active-low;
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
+
+&usbmisc1 {
+ status = "okay";
+};
+
+&usdhc0 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc0>;
+ pinctrl-1 = <&pinctrl_usdhc0>;
+ pinctrl-2 = <&pinctrl_usdhc0>;
+ pinctrl-3 = <&pinctrl_usdhc0>;
+ non-removable;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&iomuxc1 {
+ pinctrl_lpuart5: lpuart5grp {
+ fsl,pins = <
+ MX8ULP_PAD_PTF14__LPUART5_TX 0x3
+ MX8ULP_PAD_PTF15__LPUART5_RX 0x3
+ >;
+ };
+
+ pinctrl_otgid1: usb1grp {
+ fsl,pins = <
+ MX8ULP_PAD_PTE16__USB0_ID 0x10003
+ >;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ MX8ULP_PAD_PTD1__SDHC0_CMD 0x3
+ MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002
+ MX8ULP_PAD_PTD10__SDHC0_D0 0x3
+ MX8ULP_PAD_PTD9__SDHC0_D1 0x3
+ MX8ULP_PAD_PTD8__SDHC0_D2 0x3
+ MX8ULP_PAD_PTD7__SDHC0_D3 0x3
+ MX8ULP_PAD_PTD6__SDHC0_D4 0x3
+ MX8ULP_PAD_PTD5__SDHC0_D5 0x3
+ MX8ULP_PAD_PTD4__SDHC0_D6 0x3
+ MX8ULP_PAD_PTD3__SDHC0_D7 0x3
+ MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002
+ >;
+ };
+};
+
+&dsi {
+ status = "okay";
+
+ panel@0 {
+ compatible = "usmp,rm67162";
+ reg = <0>;
+ dsi-lanes = <1>;
+ reset,otherway;
+ vcc-supply = <&reg_5v>;
+ iovcc-supply = <&reg_5v>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mipi_dsi_out>;
+ };
+ };
+ };
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ mipi_dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&dcnano {
+ status = "okay";
+};
+
+&dphy {
+ status = "okay";
+};
+
+&usbotg2 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/imx8ulp.dtsi b/arch/arm/dts/imx8ulp.dtsi
index 155d29fb19..901766957d 100644
--- a/arch/arm/dts/imx8ulp.dtsi
+++ b/arch/arm/dts/imx8ulp.dtsi
@@ -157,6 +157,11 @@
reg = <0x11>;
#power-domain-cells = <1>;
};
+
+ scmi_sensor: protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <0>;
+ };
};
};
diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
new file mode 100644
index 0000000000..13474a35fc
--- /dev/null
+++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog3>;
+ u-boot,dm-spl;
+ };
+
+ aliases {
+ usbgadget0 = &usbg1;
+ usbgadget1 = &usbg2;
+ };
+
+ usbg1: usbg1 {
+ compatible = "fsl,imx27-usb-gadget";
+ dr_mode = "peripheral";
+ chipidea,usb = <&usbotg1>;
+ status = "okay";
+ };
+
+ usbg2: usbg2 {
+ compatible = "fsl,imx27-usb-gadget";
+ dr_mode = "peripheral";
+ chipidea,usb = <&usbotg2>;
+ status = "okay";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&reg_usdhc2_vmmc {
+ u-boot,off-on-delay-us = <20000>;
+ u-boot,dm-spl;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&lpuart1 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+ fsl,signal-voltage-switch-extra-delay-ms = <8>;
+};
+
+&lpi2c1 {
+ u-boot,dm-spl;
+};
+
+&lpi2c2 {
+ u-boot,dm-spl;
+};
+
+&lpi2c3 {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
+ u-boot,dm-spl;
+};
+
+&pinctrl_lpi2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_lpi2c2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_lpi2c3 {
+ u-boot,dm-spl;
+};
+
+&fec {
+ phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <15>;
+ phy-reset-post-delay = <100>;
+};
+
+&eqos {
+ compatible = "fsl,imx-eqos";
+};
+
+&ethphy1 {
+ reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <100000>;
+};
+
+&usbotg1 {
+ status = "okay";
+ extcon = <&ptn5110>;
+};
+
+&usbotg2 {
+ status = "okay";
+ extcon = <&ptn5110_2>;
+};
+
+&s4muap {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&clk {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
+};
+
+&osc_32k {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&osc_24m {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk_ext1 {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&lcdif {
+ assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, <&clk IMX93_CLK_MEDIA_APB>;
+ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+ assigned-clock-rates = <400000000>, <133333334>;
+};
diff --git a/arch/arm/dts/imx93-11x11-evk.dts b/arch/arm/dts/imx93-11x11-evk.dts
new file mode 100644
index 0000000000..38bf2aeb99
--- /dev/null
+++ b/arch/arm/dts/imx93-11x11-evk.dts
@@ -0,0 +1,624 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+/dts-v1/;
+
+#include "imx93.dtsi"
+
+/{
+ model = "NXP i.MX93 11X11 EVK board";
+ compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ aliases {
+ i2c8 = &flexio_i2c_master;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ audio: audio@a4120000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa4120000 0 0x100000>;
+ no-map;
+ };
+ };
+
+ reg_can2_stby: regulator-can2-stby {
+ compatible = "regulator-fixed";
+ regulator-name = "can2-stby";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&adp5585gpio 5 GPIO_ACTIVE_LOW>;
+ enable-active-low;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usdhc3_pwrseq: usdhc3_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ dsi_host: dsi-host {
+ compatible = "synopsys,dw-mipi-dsi";
+ status = "okay";
+ };
+
+ rm67199_panel {
+ compatible = "raydium,rm67199";
+ reset-gpio = <&adp5585gpio 6 GPIO_ACTIVE_LOW>;
+ dsi-lanes = <4>;
+ video-mode = <2>; /* 0: burst mode
+ * 1: non-burst mode with sync event
+ * 2: non-burst mode with sync pulse
+ */
+ width-mm = <68>;
+ height-mm = <121>;
+ status = "okay";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+};
+
+&dphy {
+ status = "okay";
+};
+
+&dsi {
+ status = "okay";
+
+ ports {
+ port@1 {
+ dsi_to_adv7535: endpoint {
+ remote-endpoint = <&adv7535_to_dsi>;
+ };
+ };
+
+ port@2 {
+ dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&lcdif {
+ status = "okay";
+ assigned-clock-rates = <484000000>, <121000000>, <400000000>, <133333333>;
+};
+
+&lpi2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-1 = <&pinctrl_lpi2c1>;
+ status = "okay";
+
+ adv7535: hdmi@3d {
+ compatible = "adi,adv7535";
+ reg = <0x3d>;
+ adi,addr-cec = <0x3c>;
+ adi,dsi-lanes = <4>;
+ status = "okay";
+
+ port {
+ adv7535_to_dsi: endpoint {
+ remote-endpoint = <&dsi_to_adv7535>;
+ };
+ };
+ };
+};
+
+&lpi2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-1 = <&pinctrl_lpi2c2>;
+ status = "okay";
+
+ pmic@25 {
+ compatible = "nxp,pca9451a";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ interrupt-parent = <&pcal6524>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4{
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5{
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ pcal6524: gpio@22 {
+ compatible = "nxp,pcal6524";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcal6524>;
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ adp5585gpio: gpio@34 {
+ compatible = "adp5585";
+ reg = <0x34>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&lpi2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ pinctrl-1 = <&pinctrl_lpi2c3>;
+ status = "okay";
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110";
+ reg = <0x50>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ status = "okay";
+
+ port {
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+
+ typec1_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ op-sink-microwatt = <15000000>;
+ self-powered;
+ };
+ };
+
+ ptn5110_2: tcpc@51 {
+ compatible = "nxp,ptn5110";
+ reg = <0x51>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ status = "okay";
+
+ port {
+ typec2_dr_sw: endpoint {
+ remote-endpoint = <&usb2_drd_sw>;
+ };
+ };
+
+ typec2_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ op-sink-microwatt = <15000000>;
+ self-powered;
+ };
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>;
+ clock-names = "ipg", "per";
+ status = "okay";
+};
+
+&lpuart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "disabled";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ disable-over-current;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usbotg2 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ disable-over-current;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ port {
+ usb2_drd_sw: endpoint {
+ remote-endpoint = <&typec2_dr_sw>;
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1>;
+ pinctrl-2 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&reg_usdhc2_vmmc>;
+ bus-width = <4>;
+ status = "okay";
+ no-sdio;
+ no-mmc;
+};
+
+&usdhc3 {
+ status = "disabled";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy2>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ eee-broken-1000t;
+ rtl821x,aldps-disable;
+ rtl821x,clkout-disable;
+ };
+ };
+};
+
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy1>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ eee-broken-1000t;
+ rtl821x,aldps-disable;
+ rtl821x,clkout-disable;
+ };
+ };
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <&reg_can2_stby>;
+ status = "okay";
+};
+
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi>;
+ status = "disabled";
+
+ flash0: flash@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ status = "okay";
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
+ MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
+ >;
+ };
+
+ pinctrl_flexspi: flexspigrp {
+ fsl,pins = <
+ MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x42
+ MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x42
+ MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x42
+ MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x42
+ MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x42
+ MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x42
+ MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x42
+ MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x42
+ MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x42
+ MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x42
+ MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x42
+ MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x42
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
+ MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
+ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
+ MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
+ MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
+ MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
+ MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
+ MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
+ MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
+ MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
+ MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
+ MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
+ MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
+ MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
+ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
+ MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
+ MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
+ MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
+ MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
+ MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
+ MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
+ MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
+ MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
+ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
+ MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
+ MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
+ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c3: lpi2c3grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
+ MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_pcal6524: pcal6524grp {
+ fsl,pins = <
+ MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX93_PAD_UART2_TXD__LPUART2_TX 0x31e
+ MX93_PAD_UART2_RXD__LPUART2_RX 0x31e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+};
+
+&wdog3 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx93-pinfunc.h b/arch/arm/dts/imx93-pinfunc.h
new file mode 100644
index 0000000000..4298a145f8
--- /dev/null
+++ b/arch/arm/dts/imx93-pinfunc.h
@@ -0,0 +1,623 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __DTS_IMX93_PINFUNC_H
+#define __DTS_IMX93_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
+#define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
+#define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
+#define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
+#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
+#define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03D4 0x0 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x5 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x042C 0x6 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x0 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x1 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x3 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x5 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x0434 0x6 0x0
+#define MX93_PAD_GPIO_IO00__GPIO2_IO00 0x0010 0x01C0 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03E4 0x11 0x0
+#define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x0434 0x5 0x1
+#define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03EC 0x16 0x0
+#define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0
+#define MX93_PAD_GPIO_IO01__GPIO2_IO01 0x0014 0x01C4 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E0 0x11 0x0
+#define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0430 0x5 0x1
+#define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03E8 0x16 0x0
+#define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0
+#define MX93_PAD_GPIO_IO02__GPIO2_IO02 0x0018 0x01C8 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x11 0x0
+#define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x042C 0x5 0x1
+#define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03F4 0x16 0x0
+#define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x0018 0x01C8 0x0374 0x7 0x0
+#define MX93_PAD_GPIO_IO03__GPIO2_IO03 0x001C 0x01CC 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x11 0x0
+#define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F0 0x16 0x0
+#define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x001C 0x01CC 0x0378 0x7 0x0
+#define MX93_PAD_GPIO_IO04__GPIO2_IO04 0x0020 0x01D0 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01D0 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x0020 0x01D0 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03F4 0x16 0x1
+#define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x0020 0x01D0 0x037C 0x7 0x0
+#define MX93_PAD_GPIO_IO05__GPIO2_IO05 0x0024 0x01D4 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0438 0x2 0x0
+#define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x0024 0x01D4 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F0 0x16 0x1
+#define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x0024 0x01D4 0x0380 0x7 0x0
+#define MX93_PAD_GPIO_IO06__GPIO2_IO06 0x0028 0x01D8 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x043C 0x2 0x0
+#define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x0028 0x01D8 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x03FC 0x16 0x0
+#define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x0028 0x01D8 0x0384 0x7 0x0
+#define MX93_PAD_GPIO_IO07__GPIO2_IO07 0x002C 0x01DC 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0x002C 0x01DC 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x002C 0x01DC 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x03F8 0x16 0x0
+#define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x002C 0x01DC 0x0388 0x7 0x0
+#define MX93_PAD_GPIO_IO08__GPIO2_IO08 0x0030 0x01E0 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0x0030 0x01E0 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x0030 0x01E0 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x03FC 0x16 0x1
+#define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x0030 0x01E0 0x038C 0x7 0x0
+#define MX93_PAD_GPIO_IO09__GPIO2_IO09 0x0034 0x01E4 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0x0034 0x01E4 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x0034 0x01E4 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x03F8 0x16 0x1
+#define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x0034 0x01E4 0x0390 0x7 0x0
+#define MX93_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0x0038 0x01E8 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x0038 0x01E8 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x0404 0x16 0x0
+#define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x7 0x0
+#define MX93_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0x003C 0x01EC 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x003C 0x01EC 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0400 0x16 0x0
+#define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x7 0x0
+#define MX93_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0440 0x2 0x0
+#define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x0040 0x01F0 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x0404 0x16 0x1
+#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0450 0x7 0x0
+#define MX93_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x0444 0x2 0x0
+#define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x0044 0x01F4 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0400 0x16 0x1
+#define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x7 0x0
+#define MX93_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x041C 0x1 0x0
+#define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x0048 0x01F8 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0428 0x6 0x0
+#define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x7 0x0
+#define MX93_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0418 0x1 0x0
+#define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x004C 0x01FC 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x0424 0x6 0x0
+#define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x7 0x0
+#define MX93_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0440 0x2 0x1
+#define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x0414 0x4 0x0
+#define MX93_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0420 0x6 0x0
+#define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x7 0x0
+#define MX93_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0x0054 0x0204 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x7 0x0
+#define MX93_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x044C 0x1 0x0
+#define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x0058 0x0208 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x7 0x0
+#define MX93_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0450 0x1 0x1
+#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x0444 0x2 0x1
+#define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x020C 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x005C 0x020C 0x0000 0x7 0x0
+#define MX93_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x0060 0x0210 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0438 0x2 0x1
+#define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03B4 0x7 0x0
+#define MX93_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x0064 0x0214 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x044C 0x7 0x1
+#define MX93_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0458 0x1 0x0
+#define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x0454 0x2 0x0
+#define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03EC 0x16 0x1
+#define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x7 0x0
+#define MX93_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x045C 0x1 0x0
+#define MX93_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03E8 0x16 0x1
+#define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x7 0x0
+#define MX93_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0460 0x1 0x0
+#define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x7 0x0
+#define MX93_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x0464 0x1 0x0
+#define MX93_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03D4 0x5 0x1
+#define MX93_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x7 0x0
+#define MX93_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0468 0x1 0x0
+#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x043C 0x2 0x1
+#define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03D8 0x5 0x1
+#define MX93_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x0000 0x7 0x0
+#define MX93_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x046C 0x1 0x0
+#define MX93_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x2 0x1
+#define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03DC 0x5 0x1
+#define MX93_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x7 0x0
+#define MX93_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03E4 0x11 0x1
+#define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x7 0x0
+#define MX93_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E0 0x11 0x1
+#define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x7 0x0
+#define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x0 0x0
+#define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x4 0x0
+#define MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x5 0x0
+#define MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x008C 0x023C 0x0000 0x5 0x0
+#define MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008C 0x023C 0x0000 0x0 0x0
+#define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x4 0x1
+#define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x0 0x0
+#define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x4 0x0
+#define MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x5 0x0
+#define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x0 0x0
+#define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x4 0x0
+#define MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x0098 0x0248 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03CC 0x2 0x0
+#define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x0098 0x0248 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_MDC__GPIO4_IO00 0x0098 0x0248 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D0 0x2 0x0
+#define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x009C 0x024C 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x009C 0x024C 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00A0 0x0250 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TD3__CAN2_TX 0x00A0 0x0250 0x0000 0x2 0x0
+#define MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00A0 0x0250 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 0x00A0 0x0250 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TD3__GPIO4_IO02 0x00A0 0x0250 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00A4 0x0254 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x00A4 0x0254 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_TD2__CAN2_RX 0x00A4 0x0254 0x0364 0x2 0x2
+#define MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00A4 0x0254 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 0x00A4 0x0254 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TD2__GPIO4_IO03 0x00A4 0x0254 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x00A8 0x0258 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TD1__LPUART3_RTS_B 0x00A8 0x0258 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_TD1__I3C2_PUR 0x00A8 0x0258 0x0000 0x2 0x0
+#define MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00A8 0x0258 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 0x00A8 0x0258 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TD1__GPIO4_IO04 0x00A8 0x0258 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x6 0x0
+#define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x041C 0x1 0x1
+#define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x00AC 0x025C 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TD0__GPIO4_IO05 0x00AC 0x025C 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00B0 0x0260 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 0x00B0 0x0260 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x00B0 0x0260 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00B4 0x0264 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00B4 0x0264 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 0x00B4 0x0264 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TXC__GPIO4_IO07 0x00B4 0x0264 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00B8 0x0268 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00B8 0x0268 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00B8 0x0268 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 0x00B8 0x0268 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x00B8 0x0268 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x00BC 0x026C 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00BC 0x026C 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x00BC 0x026C 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RXC__GPIO4_IO09 0x00BC 0x026C 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0418 0x1 0x1
+#define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x0414 0x1 0x1
+#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0408 0x3 0x0
+#define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x040C 0x3 0x0
+#define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x2 0x0
+#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0410 0x3 0x0
+#define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_MDC__ENET1_MDC 0x00D0 0x0280 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_MDC__LPUART4_DCB_B 0x00D0 0x0280 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00D0 0x0280 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00D0 0x0280 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_MDC__GPIO4_IO14 0x00D0 0x0280 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x00D4 0x0284 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00D4 0x0284 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00D4 0x0284 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00D4 0x0284 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x00D4 0x0284 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TD3__SAI2_RX_DATA00 0x00D8 0x0288 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00D8 0x0288 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TD3__GPIO4_IO16 0x00D8 0x0288 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x00D8 0x0288 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x00DC 0x028C 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x00DC 0x028C 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_TD2__SAI2_RX_DATA01 0x00DC 0x028C 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00DC 0x028C 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TD2__GPIO4_IO17 0x00DC 0x028C 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x00E0 0x0290 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TD1__LPUART4_RTS_B 0x00E0 0x0290 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_TD1__SAI2_RX_DATA02 0x00E0 0x0290 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x00E4 0x0294 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0428 0x1 0x1
+#define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 0x00E4 0x0294 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x00E8 0x0298 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00E8 0x0298 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00E8 0x0298 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00E8 0x0298 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00E8 0x0298 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x00EC 0x029C 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TXC__ENET1_TX_ER 0x00EC 0x029C 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00EC 0x029C 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00EC 0x029C 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TXC__GPIO4_IO21 0x00EC 0x029C 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x00F0 0x02A0 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00F0 0x02A0 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 0x00F0 0x02A0 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00F0 0x02A0 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00F0 0x02A0 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x00F4 0x02A4 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x00F4 0x02A4 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_RXC__SAI2_TX_DATA01 0x00F4 0x02A4 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x00F8 0x02A8 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x0424 0x1 0x1
+#define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 0x00F8 0x02A8 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x00FC 0x02AC 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x0454 0x1 0x1
+#define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 0x00FC 0x02AC 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x0100 0x02B0 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0420 0x1 0x1
+#define MX93_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x3 0x0
+#define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x0104 0x02B4 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x0454 0x2 0x2
+#define MX93_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x3 0x0
+#define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x5 0x0
+#define MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08 0x0108 0x02B8 0x038C 0x4 0x1
+#define MX93_PAD_SD1_CLK__GPIO3_IO08 0x0108 0x02B8 0x0000 0x5 0x0
+#define MX93_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02B8 0x0000 0x0 0x0
+#define MX93_PAD_SD1_CMD__USDHC1_CMD 0x010C 0x02BC 0x0000 0x0 0x0
+#define MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09 0x010C 0x02BC 0x0390 0x4 0x1
+#define MX93_PAD_SD1_CMD__GPIO3_IO09 0x010C 0x02BC 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02C0 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02C0 0x0394 0x4 0x1
+#define MX93_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02C0 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02C4 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02C4 0x0398 0x4 0x1
+#define MX93_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02C4 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02C4 0x0000 0x6 0x0
+#define MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02C8 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02C8 0x0000 0x4 0x0
+#define MX93_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02C8 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02C8 0x0000 0x6 0x0
+#define MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x011C 0x02CC 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011C 0x02CC 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011C 0x02CC 0x039C 0x4 0x1
+#define MX93_PAD_SD1_DATA3__GPIO3_IO13 0x011C 0x02CC 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02D0 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x0120 0x02D0 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02D0 0x03A0 0x4 0x1
+#define MX93_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02D0 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02D4 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x0124 0x02D4 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02D4 0x0000 0x2 0x0
+#define MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02D4 0x03A4 0x4 0x1
+#define MX93_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02D4 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02D8 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x0128 0x02D8 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02D8 0x0000 0x2 0x0
+#define MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02D8 0x03A8 0x4 0x1
+#define MX93_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02D8 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x012C 0x02DC 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x012C 0x02DC 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA7__USDHC1_WP 0x012C 0x02DC 0x0000 0x2 0x0
+#define MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012C 0x02DC 0x03AC 0x4 0x1
+#define MX93_PAD_SD1_DATA7__GPIO3_IO17 0x012C 0x02DC 0x0000 0x5 0x0
+#define MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02E0 0x0000 0x0 0x0
+#define MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02E0 0x0000 0x1 0x0
+#define MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02E0 0x03B0 0x4 0x1
+#define MX93_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x5 0x0
+#define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x0 0x0
+#define MX93_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x1 0x0
+#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0410 0x2 0x1
+#define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x4 0x0
+#define MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x5 0x0
+#define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x6 0x0
+#define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0458 0x0 0x1
+#define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x1 0x0
+#define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x4 0x1
+#define MX93_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x5 0x0
+#define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x045C 0x0 0x1
+#define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x1 0x0
+#define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x4 0x0
+#define MX93_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x5 0x0
+#define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0460 0x0 0x1
+#define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x0140 0x02F0 0x0000 0x1 0x0
+#define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x4 0x1
+#define MX93_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x5 0x0
+#define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x0464 0x0 0x1
+#define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x0144 0x02F4 0x0000 0x1 0x0
+#define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x4 0x1
+#define MX93_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x5 0x0
+#define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0468 0x0 0x1
+#define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x0148 0x02F8 0x0000 0x1 0x0
+#define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x4 0x1
+#define MX93_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x5 0x0
+#define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x046C 0x0 0x1
+#define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x014C 0x02FC 0x0000 0x1 0x0
+#define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x4 0x1
+#define MX93_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x5 0x0
+#define MX93_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x0 0x0
+#define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x1 0x0
+#define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03CC 0x2 0x1
+#define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x0150 0x0300 0x036C 0x4 0x1
+#define MX93_PAD_SD2_CD_B__GPIO3_IO00 0x0150 0x0300 0x0000 0x5 0x0
+#define MX93_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x0 0x0
+#define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x1 0x0
+#define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D0 0x2 0x1
+#define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x0154 0x0304 0x0370 0x4 0x1
+#define MX93_PAD_SD2_CLK__GPIO3_IO01 0x0154 0x0304 0x0000 0x5 0x0
+#define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x6 0x0
+#define MX93_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x0 0x0
+#define MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x1 0x0
+#define MX93_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x2 0x0
+#define MX93_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x3 0x0
+#define MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02 0x0158 0x0308 0x0374 0x4 0x1
+#define MX93_PAD_SD2_CMD__GPIO3_IO02 0x0158 0x0308 0x0000 0x5 0x0
+#define MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x6 0x0
+#define MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x015C 0x030C 0x0000 0x0 0x0
+#define MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT 0x015C 0x030C 0x0000 0x1 0x0
+#define MX93_PAD_SD2_DATA0__CAN2_TX 0x015C 0x030C 0x0000 0x2 0x0
+#define MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 0x015C 0x030C 0x0378 0x4 0x1
+#define MX93_PAD_SD2_DATA0__GPIO3_IO03 0x015C 0x030C 0x0000 0x5 0x0
+#define MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015C 0x030C 0x0000 0x6 0x0
+#define MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x0 0x0
+#define MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x1 0x0
+#define MX93_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x2 0x3
+#define MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 0x0160 0x0310 0x037C 0x4 0x1
+#define MX93_PAD_SD2_DATA1__GPIO3_IO04 0x0160 0x0310 0x0000 0x5 0x0
+#define MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x6 0x0
+#define MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x0 0x0
+#define MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x1 0x0
+#define MX93_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x2 0x0
+#define MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 0x0164 0x0314 0x0380 0x4 0x1
+#define MX93_PAD_SD2_DATA2__GPIO3_IO05 0x0164 0x0314 0x0000 0x5 0x0
+#define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x6 0x0
+#define MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x0 0x0
+#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0408 0x1 0x1
+#define MX93_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x2 0x0
+#define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x0168 0x0318 0x0384 0x4 0x1
+#define MX93_PAD_SD2_DATA3__GPIO3_IO06 0x0168 0x0318 0x0000 0x5 0x0
+#define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x6 0x0
+#define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x0 0x0
+#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x040C 0x1 0x1
+#define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x016C 0x031C 0x0388 0x4 0x1
+#define MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x016C 0x031C 0x0000 0x5 0x0
+#define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x6 0x0
+#define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x10 0x0
+#define MX93_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x1 0x0
+#define MX93_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x2 0x0
+#define MX93_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x3 0x0
+#define MX93_PAD_I2C1_SCL__GPIO1_IO00 0x0170 0x0320 0x0000 0x5 0x0
+#define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x10 0x0
+#define MX93_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x1 0x0
+#define MX93_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x2 0x0
+#define MX93_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x3 0x0
+#define MX93_PAD_I2C1_SDA__GPIO1_IO01 0x0174 0x0324 0x0000 0x5 0x0
+#define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x10 0x0
+#define MX93_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x1 0x0
+#define MX93_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x2 0x0
+#define MX93_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x3 0x0
+#define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x4 0x0
+#define MX93_PAD_I2C2_SCL__GPIO1_IO02 0x0178 0x0328 0x0000 0x5 0x0
+#define MX93_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x6 0x0
+#define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x10 0x0
+#define MX93_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x2 0x0
+#define MX93_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x3 0x0
+#define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x4 0x0
+#define MX93_PAD_I2C2_SDA__GPIO1_IO03 0x017C 0x032C 0x0000 0x5 0x0
+#define MX93_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0000 0x0 0x0
+#define MX93_PAD_UART1_RXD__S400_UART_RX 0x0180 0x0330 0x0000 0x1 0x0
+#define MX93_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0000 0x2 0x0
+#define MX93_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x3 0x0
+#define MX93_PAD_UART1_RXD__GPIO1_IO04 0x0180 0x0330 0x0000 0x5 0x0
+#define MX93_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x0000 0x0 0x0
+#define MX93_PAD_UART1_TXD__S400_UART_TX 0x0184 0x0334 0x0000 0x1 0x0
+#define MX93_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0000 0x2 0x0
+#define MX93_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x3 0x0
+#define MX93_PAD_UART1_TXD__GPIO1_IO05 0x0184 0x0334 0x0000 0x5 0x0
+#define MX93_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0000 0x0 0x0
+#define MX93_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0000 0x1 0x0
+#define MX93_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0000 0x2 0x0
+#define MX93_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x3 0x0
+#define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0448 0x4 0x0
+#define MX93_PAD_UART2_RXD__GPIO1_IO06 0x0188 0x0338 0x0000 0x5 0x0
+#define MX93_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0000 0x0 0x0
+#define MX93_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x1 0x0
+#define MX93_PAD_UART2_TXD__LPSPI2_SCK 0x018C 0x033C 0x0000 0x2 0x0
+#define MX93_PAD_UART2_TXD__TPM1_CH3 0x018C 0x033C 0x0000 0x3 0x0
+#define MX93_PAD_UART2_TXD__GPIO1_IO07 0x018C 0x033C 0x0000 0x5 0x0
+#define MX93_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x0 0x0
+#define MX93_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x1 0x0
+#define MX93_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x4 0x0
+#define MX93_PAD_PDM_CLK__GPIO1_IO08 0x0190 0x0340 0x0000 0x5 0x0
+#define MX93_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x6 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0438 0x0 0x2
+#define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x1 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0000 0x2 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x3 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x4 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x0194 0x0344 0x0000 0x5 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x6 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x043C 0x0 0x2
+#define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x0198 0x0348 0x0000 0x1 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0000 0x2 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x3 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x4 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x5 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x6 0x1
+#define MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019C 0x034C 0x0000 0x0 0x0
+#define MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01 0x019C 0x034C 0x0000 0x1 0x0
+#define MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019C 0x034C 0x0000 0x2 0x0
+#define MX93_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019C 0x034C 0x0000 0x3 0x0
+#define MX93_PAD_SAI1_TXFS__MQS1_LEFT 0x019C 0x034C 0x0000 0x4 0x0
+#define MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x019C 0x034C 0x0000 0x5 0x0
+#define MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01A0 0x0350 0x0000 0x0 0x0
+#define MX93_PAD_SAI1_TXC__LPUART2_CTS_B 0x01A0 0x0350 0x0000 0x1 0x0
+#define MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x01A0 0x0350 0x0000 0x2 0x0
+#define MX93_PAD_SAI1_TXC__LPUART1_DSR_B 0x01A0 0x0350 0x0000 0x3 0x0
+#define MX93_PAD_SAI1_TXC__CAN1_RX 0x01A0 0x0350 0x0360 0x4 0x1
+#define MX93_PAD_SAI1_TXC__GPIO1_IO12 0x01A0 0x0350 0x0000 0x5 0x0
+#define MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x01A4 0x0354 0x0000 0x0 0x0
+#define MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01A4 0x0354 0x0000 0x1 0x0
+#define MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x01A4 0x0354 0x0000 0x2 0x0
+#define MX93_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01A4 0x0354 0x0000 0x3 0x0
+#define MX93_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x4 0x0
+#define MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x5 0x0
+#define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x01A8 0x0358 0x0000 0x0 0x0
+#define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0448 0x1 0x1
+#define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0000 0x2 0x0
+#define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x3 0x0
+#define MX93_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x4 0x0
+#define MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x01A8 0x0358 0x0000 0x5 0x0
+#define MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01AC 0x035C 0x0000 0x0 0x0
+#define MX93_PAD_WDOG_ANY__GPIO1_IO15 0x01AC 0x035C 0x0000 0x5 0x0
+
+#endif /* __DTS_IMX93_PINFUNC_H */
diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi
new file mode 100644
index 0000000000..59a09b5ec5
--- /dev/null
+++ b/arch/arm/dts/imx93.dtsi
@@ -0,0 +1,1514 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <dt-bindings/clock/imx93-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/power/imx93-power.h>
+#include <dt-bindings/usb/pd.h>
+
+#include "imx93-pinfunc.h"
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ ethernet0 = &fec;
+ ethernet1 = &eqos;
+ serial0 = &lpuart1;
+ serial1 = &lpuart2;
+ serial2 = &lpuart3;
+ serial3 = &lpuart4;
+ serial4 = &lpuart5;
+ serial5 = &lpuart6;
+ serial6 = &lpuart7;
+ serial7 = &lpuart8;
+ isi0 = &isi_0;
+ i2c0 = &lpi2c1;
+ i2c1 = &lpi2c2;
+ i2c2 = &lpi2c3;
+ i2c3 = &lpi2c4;
+ i2c4 = &lpi2c5;
+ i2c5 = &lpi2c6;
+ i2c6 = &lpi2c7;
+ i2c7 = &lpi2c8;
+ csi0 = &mipi_csi;
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A55_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ };
+
+ A55_1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ };
+
+ };
+
+ osc_32k: clock-osc-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+ };
+
+ osc_24m: clock-osc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc_24m";
+ };
+
+ clk_ext1: clock-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext1";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24000000>;
+ arm,no-tick-in-suspend;
+ interrupt-parent = <&gic>;
+ };
+
+ gic: interrupt-controller@48000000 {
+ compatible = "arm,gic-v3";
+ reg = <0 0x48000000 0 0x10000>,
+ <0 0x48040000 0 0xc0000>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ };
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <80000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu-crit {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x80000000>,
+ <0x28000000 0x0 0x28000000 0x10000000>;
+
+ aips1: bus@44000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x44000000 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mu1: mailbox@44230000 {
+ compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
+ reg = <0x44230000 0x10000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ edma1: dma-controller@44000000{
+ compatible = "fsl,imx93-edma-v3";
+ reg = <0x44000000 0x10000>,
+ <0x44010000 0x10000>, <0x44020000 0x10000>,
+ <0x44030000 0x10000>, <0x44040000 0x10000>,
+ <0x44050000 0x10000>, <0x44060000 0x10000>,
+ <0x44070000 0x10000>, <0x44080000 0x10000>,
+ <0x44090000 0x10000>, <0x440a0000 0x10000>,
+ <0x440b0000 0x10000>, <0x440c0000 0x10000>,
+ <0x440d0000 0x10000>, <0x440e0000 0x10000>,
+ <0x440f0000 0x10000>, <0x44100000 0x10000>,
+ <0x44110000 0x10000>, <0x44120000 0x10000>,
+ <0x44130000 0x10000>, <0x44140000 0x10000>,
+ <0x44150000 0x10000>, <0x44160000 0x10000>,
+ <0x44170000 0x10000>, <0x44180000 0x10000>,
+ <0x44190000 0x10000>, <0x441a0000 0x10000>,
+ <0x441b0000 0x10000>, <0x441c0000 0x10000>,
+ <0x441d0000 0x10000>, <0x441e0000 0x10000>,
+ <0x441f0000 0x10000>;
+ #dma-cells = <3>;
+ dma-channels = <31>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma1-chan0-tx", "edma1-chan1-tx",
+ "edma1-chan2-tx", "edma1-chan3-tx",
+ "edma1-chan4-tx", "edma1-chan5-tx",
+ "edma1-chan6-tx", "edma1-chan7-tx",
+ "edma1-chan8-tx", "edma1-chan9-tx",
+ "edma1-chan10-tx", "edma1-chan11-tx",
+ "edma1-chan12-tx", "edma1-chan13-tx",
+ "edma1-chan14-tx", "edma1-chan15-tx",
+ "edma1-chan16-tx", "edma1-chan17-tx",
+ "edma1-chan18-tx", "edma1-chan19-tx",
+ "edma1-chan20-tx", "edma1-chan21-tx",
+ "edma1-chan22-tx", "edma1-chan23-tx",
+ "edma1-chan24-tx", "edma1-chan25-tx",
+ "edma1-chan26-tx", "edma1-chan27-tx",
+ "edma1-chan28-tx", "edma1-chan29-tx",
+ "edma1-chan30-tx", "edma1-err";
+ clocks = <&clk IMX93_CLK_EDMA1_GATE>;
+ clock-names = "edma";
+ status = "disabled";
+ };
+
+ anomix_ns_gpr: blk-ctrl-anomix@42420000 {
+ compatible = "syscon";
+ reg = <0x44210000 0x1000>;
+ };
+
+ system_counter: timer@44290000 {
+ compatible = "nxp,sysctr-timer";
+ reg = <0x44290000 0x30000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc_24m>;
+ clock-names = "per";
+ };
+
+ i3c1: i3c-master@44330000 {
+ #address-cells = <3>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master";
+ reg = <0x44330000 0x10000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_I3C1_GATE>,
+ <&clk IMX93_CLK_I3C1_GATE>,
+ <&clk IMX93_CLK_DUMMY>;
+ clock-names = "pclk", "fast_clk", "slow_clk";
+ status = "disabled";
+ };
+
+ lpi2c1: i2c@44340000 {
+ compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x44340000 0x10000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
+ <&clk IMX93_CLK_LPI2C1_GATE>;
+ clock-names = "per", "ipg";
+ dmas = <&edma1 7 0 0>, <&edma1 8 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpi2c2: i2c@44350000 {
+ compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x44350000 0x10000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
+ <&clk IMX93_CLK_LPI2C2_GATE>;
+ clock-names = "per", "ipg";
+ dmas = <&edma1 9 0 0>, <&edma1 10 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpspi1: spi@44360000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x44360000 0x10000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
+ <&clk IMX93_CLK_LPSPI1_GATE>;
+ clock-names = "per", "ipg";
+ dmas = <&edma1 11 0 0>, <&edma1 12 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpspi2: spi@44370000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x44370000 0x10000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
+ <&clk IMX93_CLK_LPSPI2_GATE>;
+ clock-names = "per", "ipg";
+ dmas = <&edma1 13 0 0>, <&edma1 14 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpuart1: serial@44380000 {
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+ reg = <0x44380000 0x1000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPUART1_GATE>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart2: serial@44390000 {
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+ reg = <0x44390000 0x1000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPUART2_GATE>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ flexcan1: can@443a0000 {
+ compatible = "fsl,imx93-flexcan", "fsl,imx8mp-flexcan";
+ reg = <0x443a0000 0x10000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_BUS_AON>,
+ <&clk IMX93_CLK_CAN1_GATE>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX93_CLK_CAN1>;
+ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+ assigned-clock-rates = <40000000>;
+ fsl,clk-source = /bits/ 8 <0>;
+ //fsl,stop-mode = <&gpr 0x10 4 0x10 20>;
+ status = "disabled";
+ };
+
+ sai1: sai@443b0000 {
+ compatible = "fsl,imx93-sai";
+ reg = <0x443b0000 0x10000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&edma1 22 0 1>, <&edma1 21 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ /* sai1 supports 2x TX/RX */
+ };
+
+ mqs1: mqs1 {
+ compatible = "fsl,imx93-mqs";
+ gpr = <&anomix_ns_gpr>;
+ status = "disabled";
+ };
+
+ mqs2: mqs2 {
+ compatible = "fsl,imx93-mqs";
+ gpr = <&wakeupmix_gpr>;
+ status = "disabled";
+ };
+
+ iomuxc: pinctrl@443c0000 {
+ compatible = "fsl,imx93-iomuxc";
+ reg = <0x443c0000 0x10000>;
+ };
+
+ bbnsm: bbnsm@44440000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x44440000 0x10000>;
+
+ bbnsm_rtc: rtc {
+ compatible = "nxp,bbnsm-rtc";
+ regmap = <&bbnsm>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ bbnsm_pwrkey: pwrkey {
+ compatible = "nxp,bbnsm-pwrkey";
+ regmap = <&bbnsm>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ linux,keycode = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ clk: clock-controller@44450000 {
+ compatible = "fsl,imx93-ccm";
+ reg = <0x44450000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
+ clock-names = "osc_32k", "osc_24m", "clk_ext1";
+ assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <393216000>;
+ status = "okay";
+ };
+
+ src: src@44460000 {
+ compatible = "fsl,imx93-src";
+ reg = <0x44460000 0x10000>;
+
+ slice {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mlmix: slice@1800 {
+ reg = <IMX93_POWER_DOMAIN_MLMIX>;
+ #power-domain-cells = <0>;
+ };
+
+ mediamix: slice@2400 {
+ reg = <IMX93_POWER_DOMAIN_MEDIAMIX>;
+ #power-domain-cells = <0>;
+ clocks = <&clk IMX93_CLK_MEDIA_AXI>,
+ <&clk IMX93_CLK_MEDIA_APB>;
+ };
+ };
+ };
+
+ anatop: anatop@44480000 {
+ compatible = "fsl,imx93-anatop", "syscon";
+ reg = <0x44480000 0x10000>;
+ };
+
+ tmu: tmu@44482000 {
+ compatible = "fsl,imx93-tmu", "fsl,imx8mq-tmu";
+ little-endian;
+ reg = <0x44482000 0x1000>;
+ clocks = <&clk IMX93_CLK_TMC_GATE>;
+ fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
+ fsl,tmu-calibration = <0x00000000 0x00000023
+ 0x00000001 0x00000029
+ 0x00000002 0x0000002f
+ 0x00000003 0x00000035
+ 0x00000004 0x0000003d
+ 0x00000005 0x00000043
+ 0x00000006 0x0000004b
+ 0x00000007 0x00000051
+ 0x00000008 0x00000057
+ 0x00000009 0x0000005f
+ 0x0000000a 0x00000067
+ 0x0000000b 0x0000006f
+
+ 0x00010000 0x0000001b
+ 0x00010001 0x00000023
+ 0x00010002 0x0000002b
+ 0x00010003 0x00000033
+ 0x00010004 0x0000003b
+ 0x00010005 0x00000043
+ 0x00010006 0x0000004b
+ 0x00010007 0x00000055
+ 0x00010008 0x0000005d
+ 0x00010009 0x00000067
+ 0x0001000a 0x00000070
+
+ 0x00020000 0x00000017
+ 0x00020001 0x00000023
+ 0x00020002 0x0000002d
+ 0x00020003 0x00000037
+ 0x00020004 0x00000041
+ 0x00020005 0x0000004b
+ 0x00020006 0x00000057
+ 0x00020007 0x00000063
+ 0x00020008 0x0000006f
+
+ 0x00030000 0x00000015
+ 0x00030001 0x00000021
+ 0x00030002 0x0000002d
+ 0x00030003 0x00000039
+ 0x00030004 0x00000045
+ 0x00030005 0x00000053
+ 0x00030006 0x0000005f
+ 0x00030007 0x00000071>;
+ #thermal-sensor-cells = <0>;
+ status = "disabled";
+ };
+
+ micfil: micfil@44520000 {
+ compatible = "fsl,imx93-micfil";
+ reg = <0x44520000 0x10000>;
+ /*
+ 199 pdm ipi_int_hwvad_err
+ 200 pdm ipi_int_hwvad_event
+ 201 pdm ipi_int_mic_err
+ 202 pdm ipi_int_mic_filter
+ */
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_BUS_AON>,
+ <&clk IMX93_CLK_PDM_GATE>,
+ <&clk IMX93_CLK_AUDIO_PLL>,
+ <&clk IMX93_CLK_DUMMY>;
+ clock-names = "ipg_clk", "ipg_clk_app",
+ "pll8k", "clkext3";
+ dmas = <&edma1 29 0 5>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
+ adc1: adc@44530000 {
+ compatible = "nxp,imx93-adc";
+ reg = <0x44530000 0x10000>;
+ interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_ADC1_GATE>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+ };
+
+ aips2: bus@42000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x42000000 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ edma2: dma-controller@42000000{
+ compatible = "fsl,imx93-edma-v4";
+ reg = <0x42000000 0x10000>,
+ <0x42010000 0x8000>, <0x42018000 0x8000>,
+ <0x42020000 0x8000>, <0x42028000 0x8000>,
+ <0x42030000 0x8000>, <0x42038000 0x8000>,
+ <0x42040000 0x8000>, <0x42048000 0x8000>,
+ <0x42050000 0x8000>, <0x42058000 0x8000>,
+ <0x42060000 0x8000>, <0x42068000 0x8000>,
+ <0x42070000 0x8000>, <0x42078000 0x8000>,
+ <0x42080000 0x8000>, <0x42088000 0x8000>,
+ <0x42090000 0x8000>, <0x42098000 0x8000>,
+ <0x420a0000 0x8000>, <0x420a8000 0x8000>,
+ <0x420b0000 0x8000>, <0x420b8000 0x8000>,
+ <0x420c0000 0x8000>, <0x420c8000 0x8000>,
+ <0x420d0000 0x8000>, <0x420d8000 0x8000>,
+ <0x420e0000 0x8000>, <0x420e8000 0x8000>,
+ <0x420f0000 0x8000>, <0x420f8000 0x8000>,
+ <0x42100000 0x8000>, <0x42108000 0x8000>,
+ <0x42110000 0x8000>, <0x42118000 0x8000>,
+ <0x42120000 0x8000>, <0x42128000 0x8000>,
+ <0x42130000 0x8000>, <0x42138000 0x8000>,
+ <0x42140000 0x8000>, <0x42148000 0x8000>,
+ <0x42150000 0x8000>, <0x42158000 0x8000>,
+ <0x42160000 0x8000>, <0x42168000 0x8000>,
+ <0x42170000 0x8000>, <0x42178000 0x8000>,
+ <0x42180000 0x8000>, <0x42188000 0x8000>,
+ <0x42190000 0x8000>, <0x42198000 0x8000>,
+ <0x421a0000 0x8000>, <0x421a8000 0x8000>,
+ <0x421b0000 0x8000>, <0x421b8000 0x8000>,
+ <0x421c0000 0x8000>, <0x421c8000 0x8000>,
+ <0x421d0000 0x8000>, <0x421d8000 0x8000>,
+ <0x421e0000 0x8000>, <0x421e8000 0x8000>,
+ <0x421f0000 0x8000>, <0x421f8000 0x8000>,
+ <0x42200000 0x8000>, <0x42208000 0x8000>;
+ #dma-cells = <3>;
+ shared-interrupt;
+ dma-channels = <64>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma2-chan0-tx", "edma2-chan1-tx",
+ "edma2-chan2-tx", "edma2-chan3-tx",
+ "edma2-chan4-tx", "edma2-chan5-tx",
+ "edma2-chan6-tx", "edma2-chan7-tx",
+ "edma2-chan8-tx", "edma2-chan9-tx",
+ "edma2-chan10-tx", "edma2-chan11-tx",
+ "edma2-chan12-tx", "edma2-chan13-tx",
+ "edma2-chan14-tx", "edma2-chan15-tx",
+ "edma2-chan16-tx", "edma2-chan17-tx",
+ "edma2-chan18-tx", "edma2-chan19-tx",
+ "edma2-chan20-tx", "edma2-chan21-tx",
+ "edma2-chan22-tx", "edma2-chan23-tx",
+ "edma2-chan24-tx", "edma2-chan25-tx",
+ "edma2-chan26-tx", "edma2-chan27-tx",
+ "edma2-chan28-tx", "edma2-chan29-tx",
+ "edma2-chan30-tx", "edma2-chan31-tx",
+ "edma2-chan32-tx", "edma2-chan33-tx",
+ "edma2-chan34-tx", "edma2-chan35-tx",
+ "edma2-chan36-tx", "edma2-chan37-tx",
+ "edma2-chan38-tx", "edma2-chan39-tx",
+ "edma2-chan40-tx", "edma2-chan41-tx",
+ "edma2-chan42-tx", "edma2-chan43-tx",
+ "edma2-chan44-tx", "edma2-chan45-tx",
+ "edma2-chan46-tx", "edma2-chan47-tx",
+ "edma2-chan48-tx", "edma2-chan49-tx",
+ "edma2-chan50-tx", "edma2-chan51-tx",
+ "edma2-chan52-tx", "edma2-chan53-tx",
+ "edma2-chan54-tx", "edma2-chan55-tx",
+ "edma2-chan56-tx", "edma2-chan57-tx",
+ "edma2-chan58-tx", "edma2-chan59-tx",
+ "edma2-chan60-tx", "edma2-chan61-tx",
+ "edma2-chan62-tx", "edma2-chan63-tx",
+ "edma2-err";
+ clocks = <&clk IMX93_CLK_EDMA2_GATE>;
+ clock-names = "edma";
+ status = "disabled";
+ };
+
+ wakeupmix_gpr: blk-ctrl-wakeupmix@42420000 {
+ compatible = "syscon";
+ reg = <0x42420000 0x1000>;
+ };
+
+ mu2: mailbox@42440000 {
+ compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
+ reg = <0x42440000 0x10000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ wdog3: wdog@42490000 {
+ compatible = "fsl,imx93-wdt";
+ reg = <0x42490000 0x10000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_WDOG3_GATE>;
+ timeout-sec = <40>;
+ status = "disabled";
+ };
+
+ tpm4: pwm@424f0000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x424f0000 0x1000>;
+ clocks = <&clk IMX93_CLK_TPM4_GATE>;
+ assigned-clocks = <&clk IMX93_CLK_TPM4>;
+ assigned-clock-parents = <&clk IMX93_CLK_24M>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ i3c2: i3c-master@42520000 {
+ #address-cells = <3>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master";
+ reg = <0x42520000 0x10000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_I3C2_GATE>,
+ <&clk IMX93_CLK_I3C2_GATE>,
+ <&clk IMX93_CLK_DUMMY>;
+ clock-names = "pclk", "fast_clk", "slow_clk";
+ status = "disabled";
+ };
+
+ lpi2c3: i2c@42530000 {
+ compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x42530000 0x10000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
+ <&clk IMX93_CLK_LPI2C3_GATE>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 8 0 0>, <&edma2 9 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpi2c4: i2c@42540000 {
+ compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x42540000 0x10000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
+ <&clk IMX93_CLK_LPI2C4_GATE>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 10 0 0>, <&edma2 11 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpspi3: spi@42550000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x42550000 0x10000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
+ <&clk IMX93_CLK_LPSPI3_GATE>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 12 0 0>, <&edma2 13 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpspi4: spi@42560000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x42560000 0x10000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
+ <&clk IMX93_CLK_LPSPI4_GATE>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 14 0 0>, <&edma2 15 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpuart3: serial@42570000 {
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+ reg = <0x42570000 0x1000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPUART3_GATE>;
+ clock-names = "ipg";
+ dmas = <&edma2 17 0 0>, <&edma2 18 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpuart4: serial@42580000 {
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+ reg = <0x42580000 0x1000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPUART4_GATE>;
+ clock-names = "ipg";
+ dmas = <&edma2 19 0 0>, <&edma2 20 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpuart5: serial@42590000 {
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+ reg = <0x42590000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPUART5_GATE>;
+ clock-names = "ipg";
+ dmas = <&edma2 21 0 0>, <&edma2 22 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpuart6: serial@425a0000 {
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+ reg = <0x425a0000 0x1000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPUART6_GATE>;
+ clock-names = "ipg";
+ dmas = <&edma2 23 0 0>, <&edma2 24 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ flexcan2: can@425b0000 {
+ compatible = "fsl,imx93-flexcan", "fsl,imx8mp-flexcan";
+ reg = <0x425b0000 0x10000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
+ <&clk IMX93_CLK_CAN2_GATE>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX93_CLK_CAN2>;
+ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+ assigned-clock-rates = <40000000>;
+ fsl,clk-source = /bits/ 8 <0>;
+ //fsl,stop-mode = <&gpr 0x10 4 0x10 20>;
+ status = "disabled";
+ };
+
+ flexspi: spi@425e0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imx8mm-fspi";
+ reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_DUMMY>;
+ clock-names = "fspi", "fspi_en";
+ status = "disabled";
+ };
+
+ sai2: sai@42650000 {
+ compatible = "fsl,imx93-sai";
+ reg = <0x42650000 0x10000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_SAI2_GATE>,
+ <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&edma1 59 0 1>, <&edma1 58 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai3: sai@42660000 {
+ compatible = "fsl,imx93-sai";
+ reg = <0x42660000 0x10000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_SAI3_GATE>,
+ <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&edma2 61 0 1>, <&edma2 60 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spdif: spdif@42680000 {
+ compatible = "fsl,imx93-spdif";
+ reg = <0x42680000 0x800>,
+ <0x42680800 0x400>,
+ <0x42680c00 0x080>,
+ <0x42680e00 0x080>;
+ reg-names = "ram", "regs", "rxfifo",
+ "txfifo";
+ interrupts = /* XCVR IRQ 0 */
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ /* XCVR IRQ 1 */
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ /* XCVR PHY - SPDIF wakeup IRQ */
+ clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
+ <&clk IMX93_CLK_SPDIF_GATE>,
+ <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_AUD_XCVR_GATE>;
+ clock-names = "ipg", "phy", "spba", "pll_ipg";
+ dmas = <&edma2 65 0 1>, <&edma2 66 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ lpuart7: serial@42690000 {
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+ reg = <0x42690000 0x1000>;
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPUART7_GATE>;
+ clock-names = "ipg";
+ dmas = <&edma2 87 0 0>, <&edma2 88 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpuart8: serial@426a0000 {
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+ reg = <0x426a0000 0x1000>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPUART8_GATE>;
+ clock-names = "ipg";
+ dmas = <&edma2 89 0 0>, <&edma2 90 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpi2c5: i2c@426b0000 {
+ compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x426b0000 0x10000>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
+ <&clk IMX93_CLK_LPI2C5_GATE>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 71 0 0>, <&edma2 72 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpi2c6: i2c@426c0000 {
+ compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x426c0000 0x10000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
+ <&clk IMX93_CLK_LPI2C6_GATE>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 73 0 0>, <&edma2 74 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpi2c7: i2c@426d0000 {
+ compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x426d0000 0x10000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPI2C7_GATE>,
+ <&clk IMX93_CLK_LPI2C7_GATE>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 75 0 0>, <&edma2 76 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpi2c8: i2c@426e0000 {
+ compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x426e0000 0x10000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPI2C8_GATE>,
+ <&clk IMX93_CLK_LPI2C8_GATE>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 77 0 0>, <&edma2 78 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpspi5: spi@426f0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x426f0000 0x10000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI5_GATE>,
+ <&clk IMX93_CLK_LPSPI5_GATE>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 79 0 0>, <&edma2 80 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpspi6: spi@42700000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x42700000 0x10000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI6_GATE>,
+ <&clk IMX93_CLK_LPSPI6_GATE>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 81 0 0>, <&edma2 82 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpspi7: spi@42710000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x42710000 0x10000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI7_GATE>,
+ <&clk IMX93_CLK_LPSPI7_GATE>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 83 0 0>, <&edma2 84 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ lpspi8: spi@42720000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x42720000 0x10000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI8_GATE>,
+ <&clk IMX93_CLK_LPSPI8_GATE>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 85 0 0>, <&edma2 86 0 1>;
+ dma-names = "tx","rx";
+ status = "disabled";
+ };
+
+ flexio_i2c_master: flexio@425c0000 {
+ compatible = "imx,flexio_i2c_master";
+ reg = <0x425c0000 0x10000>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_FLEXIO1_GATE>,
+ <&clk IMX93_CLK_FLEXIO1_GATE>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX93_CLK_FLEXIO1_GATE>;
+ assigned-clock-parents = <&clk IMX93_CLK_FLEXIO1>;
+ assigned-clock-rates = <24000000>;
+ status = "disabled";
+ };
+ };
+
+ aips3: bus@42800000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x42800000 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usdhc1: mmc@42850000 {
+ compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
+ reg = <0x42850000 0x10000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_USDHC1_GATE>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <8>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc2: mmc@42860000 {
+ compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
+ reg = <0x42860000 0x10000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_USDHC2_GATE>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ fec: ethernet@42890000 {
+ compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec";
+ reg = <0x42890000 0x10000>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_WAKEUP_AXI>,
+ <&clk IMX93_CLK_WAKEUP_AXI>,
+ <&clk IMX93_CLK_ENET_TIMER1>,
+ <&clk IMX93_CLK_ENET_REF>,
+ <&clk IMX93_CLK_ENET_REF_PHY>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
+ <&clk IMX93_CLK_ENET_REF>,
+ <&clk IMX93_CLK_ENET_REF_PHY>;
+ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
+ <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
+ <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+ assigned-clock-rates = <100000000>, <250000000>, <50000000>;
+ fsl,num-tx-queues = <3>;
+ fsl,num-rx-queues = <3>;
+ fsl,wakeup_irq = <2>;
+ status = "disabled";
+ };
+
+ eqos: ethernet@428a0000 {
+ compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
+ reg = <0x428a0000 0x10000>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eth_wake_irq", "macirq";
+ clocks = <&clk IMX93_CLK_WAKEUP_AXI>,
+ <&clk IMX93_CLK_WAKEUP_AXI>,
+ <&clk IMX93_CLK_ENET_TIMER2>,
+ <&clk IMX93_CLK_ENET>,
+ <&clk IMX93_CLK_WAKEUP_AXI>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
+ assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
+ <&clk IMX93_CLK_ENET>;
+ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
+ <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
+ assigned-clock-rates = <100000000>, <250000000>;
+ intf_mode = <&wakeupmix_gpr 0x28>;
+ clk_csr = <0>;
+ status = "disabled";
+ };
+
+ usdhc3: mmc@428b0000 {
+ compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
+ reg = <0x428b0000 0x10000>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_USDHC3_GATE>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ epxp: epxp@4ae20000 {
+ compatible = "fsl,imx93-pxp-dma", "fsl,imx8ulp-pxp-dma";
+ reg = <0x4ae20000 0x10000>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_MEDIA_APB>,
+ <&clk IMX93_CLK_MEDIA_AXI>;
+ clock-names = "pxp_ipg", "pxp_axi";
+ pxp-gpr = <&media_blk_ctrl>;
+ power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_PXP>;
+ status = "disabled";
+ };
+
+ cameradev: camera {
+ compatible = "fsl,mxc-md", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ isi_0: isi@4ae40000{
+ compatible = "fsl,imx93-isi", "fsl,imx8-isi";
+ reg = <0x4ae40000 0x10000>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_ISI_GATE>,
+ <&clk IMX93_CLK_MEDIA_AXI>;
+ clock-names = "per", "axi";
+ assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>,
+ <&clk IMX93_CLK_MEDIA_APB>;
+ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>,
+ <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+ assigned-clock-rates = <400000000>, <133333333>;
+ interface = <2 0 2>;
+ no-reset-control;
+ power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_ISI>;
+ gasket = <&media_blk_ctrl>;
+ status = "disabled";
+
+ cap_device {
+ compatible = "imx-isi-capture";
+ status = "disabled";
+ };
+ };
+
+ mipi_csi: csi@4ae00000 {
+ compatible = "fsl,dwc-mipi-csi2-host";
+ reg = <0x4ae00000 0x10000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_MIPI_CSI_GATE>,
+ <&clk IMX93_CLK_CAM_PIX>,
+ <&clk IMX93_CLK_MIPI_PHY_CFG>;
+ clock-names = "clk_core", "clk_pixel", "phy_cfg";
+ assigned-clocks = <&clk IMX93_CLK_CAM_PIX>,
+ <&clk IMX93_CLK_MIPI_PHY_CFG>;
+ assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>,
+ <&clk IMX93_CLK_24M>;
+ assigned-clock-rates = <140000000>, <24000000>;
+ gasket = <&media_blk_ctrl>;
+ power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_CSI>;
+ status = "disabled";
+ };
+ };
+ };
+
+ gpio2: gpio@43810000 {
+ compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+ reg = <0x43810080 0x1000>, <0x43810040 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ /*
+ clocks = <&clk IMX93_CLK_RGPIO2>,
+ <&clk IMX93_CLK_PCTL2>;
+ clock-names = "gpio", "port";
+ */
+ gpio-ranges = <&iomuxc 0 32 32>;
+ };
+
+ gpio3: gpio@43820000 {
+ compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+ reg = <0x43820080 0x1000>, <0x43820040 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ /*
+ clocks = <&clk IMX93_CLK_RGPIO3>,
+ <&clk IMX93_CLK_PCTL3>;
+ clock-names = "gpio", "port";
+ */
+ gpio-ranges = <&iomuxc 0 64 32>;
+ };
+
+ gpio4: gpio@43830000 {
+ compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+ reg = <0x43830080 0x1000>, <0x43830040 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ /*
+ clocks = <&clk IMX93_CLK_RGPIO4>,
+ <&clk IMX93_CLK_PCTL4>;
+ clock-names = "gpio", "port";
+ */
+ gpio-ranges = <&iomuxc 0 96 32>;
+ };
+
+ gpio1: gpio@47400000 {
+ compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+ reg = <0x47400080 0x1000>, <0x47400040 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ /*
+ clocks = <&clk IMX93_CLK_RGPIO1>,
+ <&clk IMX93_CLK_PCTL1>;
+ clock-names = "gpio", "port";
+ */
+ gpio-ranges = <&iomuxc 0 0 32>;
+ };
+
+ ocotp: efuse@47510000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,imx93-ocotp", "syscon";
+ reg = <0x47510000 0x1000>;
+ status = "disabled";
+ };
+
+ s4muap: s4muap@47520000 {
+ compatible = "fsl,imx93-mu-s4";
+ reg = <0x47520000 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "txirq", "rxirq";
+ #mbox-cells = <2>;
+ status = "okay";
+ };
+
+ sentnl_mu: sentnl-mu {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,imx-sentnl";
+ mboxes = <&s4muap 0 0 &s4muap 1 0>;
+ mbox-names = "tx", "rx";
+ fsl,sentnl_mu_id = <2>;
+ fsl,sentnl_mu_max_users = <4>;
+ status = "okay";
+ dma-ranges = <0x80000000 0x80000000 0x20000000>;
+ };
+
+ media_blk_ctrl: blk-ctrl@4ac10000 {
+ compatible = "fsl,imx93-media-blk-ctrl", "syscon", "simple-mfd";
+ reg = <0x4ac10000 0x10000>;
+ power-domains = <&mediamix>;
+ clocks = <&clk IMX93_CLK_MEDIA_APB>,
+ <&clk IMX93_CLK_MEDIA_AXI>,
+ <&clk IMX93_CLK_NIC_MEDIA_GATE>,
+ <&clk IMX93_CLK_MEDIA_DISP_PIX>,
+ <&clk IMX93_CLK_CAM_PIX>,
+ <&clk IMX93_CLK_PXP_GATE>,
+ <&clk IMX93_CLK_LCDIF_GATE>,
+ <&clk IMX93_CLK_ISI_GATE>,
+ <&clk IMX93_CLK_MIPI_CSI_GATE>,
+ <&clk IMX93_CLK_MIPI_DSI_GATE>;
+ clock-names = "apb", "axi", "nic", "disp", "cam",
+ "pxp", "lcdif", "isi", "csi", "dsi";
+ #power-domain-cells = <1>;
+
+ dphy: dphy {
+ compatible = "fsl,imx93-mipi-dphy";
+ clocks = <&clk IMX93_CLK_MIPI_PHY_CFG>,
+ <&clk IMX93_CLK_24M>;
+ clock-names = "phy_cfg", "phy_ref";
+ assigned-clocks = <&clk IMX93_CLK_MIPI_PHY_CFG>;
+ assigned-clock-parents = <&clk IMX93_CLK_24M>;
+ assigned-clock-rates = <24000000>;
+ #phy-cells = <0>;
+ power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>;
+ status = "disabled";
+ };
+ };
+
+ ldb: ldb@4ac10020 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-ldb";
+ clocks = <&clk IMX93_CLK_LVDS_GATE>;
+ clock-names = "ldb";
+ assigned-clocks = <&clk IMX93_CLK_MEDIA_LDB>;
+ assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>;
+ gpr = <&media_blk_ctrl>;
+ power-domains = <&mediamix>;
+ status = "disabled";
+
+ lvds-channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ phys = <&ldb_phy1>;
+ phy-names = "ldb_phy";
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ ldb_ch0: endpoint {
+ remote-endpoint = <&lcdif_to_ldb>;
+ };
+ };
+ };
+ };
+
+ ldb_phy: phy@4ac10024 {
+ compatible = "fsl,imx93-lvds-phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpr = <&media_blk_ctrl>;
+ clocks = <&clk IMX93_CLK_MEDIA_APB>;
+ clock-names = "apb";
+ power-domains = <&mediamix>;
+ status = "disabled";
+
+ ldb_phy1: port@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
+
+ dsi: dsi@4ae10000 {
+ compatible = "fsl,imx93-mipi-dsi";
+ reg = <0x4ae10000 0x4000>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_MIPI_TEST_BYTE>,
+ <&clk IMX93_CLK_MIPI_DSI_GATE>;
+ clock-names = "byte", "pclk";
+ assigned-clocks = <&clk IMX93_CLK_MIPI_TEST_BYTE>,
+ <&clk IMX93_CLK_MEDIA_APB>;
+ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD0>,
+ <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+ assigned-clock-rates = <20000000>, <133333334>;
+ phys = <&dphy>;
+ phy-names = "dphy";
+ power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dsi_to_lcdif: endpoint {
+ remote-endpoint = <&lcdif_to_dsi>;
+ };
+ };
+ };
+ };
+
+ lcdif: lcd-controller@4ae30000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-lcdif";
+ reg = <0x4ae30000 0x10000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,gpr = <&media_blk_ctrl>;
+ clocks = <&clk IMX93_CLK_MEDIA_DISP_PIX>,
+ <&clk IMX93_CLK_MEDIA_AXI>,
+ <&clk IMX93_CLK_LCDIF_GATE>;
+ clock-names = "pix", "disp-axi", "disp-apb";
+ assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>,
+ <&clk IMX93_CLK_MEDIA_DISP_PIX>,
+ <&clk IMX93_CLK_MEDIA_AXI>,
+ <&clk IMX93_CLK_MEDIA_APB>;
+ assigned-clock-parents = <&clk IMX93_CLK_24M>,
+ <&clk IMX93_CLK_VIDEO_PLL>,
+ <&clk IMX93_CLK_SYS_PLL_PFD1>,
+ <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+ power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_LCDIF>;
+ status = "disabled";
+
+ lcdif_disp: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ lcdif_to_dsi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi_to_lcdif>;
+ };
+
+ lcdif_to_ldb: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&ldb_ch0>;
+ };
+ };
+ };
+
+ ddr-pmu@4e300dc0 {
+ compatible = "fsl,imx93-ddr-pmu";
+ reg = <0x4e300dc0 0x200>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ usbphynop1: usbphynop1 {
+ compatible = "usb-nop-xceiv";
+ clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
+ clock-names = "main_clk";
+ };
+
+ usbotg1: usb@4c100000 {
+ compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+ reg = <0x4c100000 0x200>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
+ clock-names = "usb1_ctrl_root_clk";
+ assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
+ assigned-clock-parents = <&clk IMX93_CLK_HSIO>;
+ fsl,usbphy = <&usbphynop1>;
+ fsl,usbmisc = <&usbmisc1 0>;
+ status = "disabled";
+ };
+
+ usbmisc1: usbmisc@4c100200 {
+ compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
+ #index-cells = <1>;
+ reg = <0x4c100200 0x200>;
+ };
+
+ usbphynop2: usbphynop2 {
+ compatible = "usb-nop-xceiv";
+ clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
+ clock-names = "main_clk";
+ };
+
+ usbotg2: usb@4c200000 {
+ compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+ reg = <0x4c200000 0x200>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
+ clock-names = "usb2_ctrl_root_clk";
+ assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
+ assigned-clock-parents = <&clk IMX93_CLK_HSIO>;
+ fsl,usbphy = <&usbphynop2>;
+ fsl,usbmisc = <&usbmisc2 0>;
+ status = "disabled";
+ };
+
+ usbmisc2: usbmisc@4c200200 {
+ compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
+ #index-cells = <1>;
+ reg = <0x4c200200 0x200>;
+ };
+ };
+
+ display-subsystem {
+ compatible = "fsl,imx-display-subsystem";
+ ports = <&lcdif_disp>;
+ };
+};
diff --git a/arch/arm/dts/ls1021a-twr-u-boot.dtsi b/arch/arm/dts/ls1021a-twr-u-boot.dtsi
new file mode 100644
index 0000000000..3711e42419
--- /dev/null
+++ b/arch/arm/dts/ls1021a-twr-u-boot.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2022 NXP
+ */
+
+&{/soc} {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
+&sec_jr3 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi
index bf96af7e36..82df2f11bb 100644
--- a/arch/arm/dts/ls1021a-twr.dtsi
+++ b/arch/arm/dts/ls1021a-twr.dtsi
@@ -6,6 +6,7 @@
*/
#include "ls1021a.dtsi"
+#include "ls1021a-twr-u-boot.dtsi"
/ {
model = "LS1021A TWR Board";
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 63bb3fb2bf..f326c90312 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -61,6 +61,7 @@
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
+#define MXC_CPU_IMX93 0xC1 /* dummy ID */
#define MXC_SOC_MX6 0x60
#define MXC_SOC_MX7 0x70
@@ -68,6 +69,7 @@
#define MXC_SOC_IMX8 0x90 /* dummy */
#define MXC_SOC_IMXRT 0xB0 /* dummy */
#define MXC_SOC_MX7ULP 0xE0 /* dummy */
+#define MXC_SOC_IMX9 0xC0 /* dummy */
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_1 0x11
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h
index 0f1e832c03..5e4fbecf05 100644
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -724,6 +724,8 @@ void ddrphy_init_read_msg_block(enum fw_type type);
void update_umctl2_rank_space_setting(unsigned int pstat_num);
void get_trained_CDD(unsigned int fsp);
+ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr);
+
static inline void reg32_write(unsigned long addr, u32 val)
{
writel(val, addr);
@@ -740,9 +742,9 @@ static inline void reg32setbit(unsigned long addr, u32 bit)
}
#define dwc_ddrphy_apb_wr(addr, data) \
- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data)
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data)
#define dwc_ddrphy_apb_rd(addr) \
- reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))
+ reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
extern struct dram_cfg_param ddrphy_trained_csr[];
extern uint32_t ddrphy_trained_csr_num;
diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
index f8115ce3fa..e07012e7d6 100644
--- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
@@ -67,6 +67,8 @@
#define FEC_QUIRK_ENET_MAC
+#define IMG_CONTAINER_BASE (0x22010000UL)
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
diff --git a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h
index b002970fd8..3638f0db53 100644
--- a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h
+++ b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h
@@ -30,6 +30,7 @@ enum {
IMX8ULP_PAD_PTC8__FLEXSPI0_A_DATA2 = IOMUX_PAD(0x0120, 0x0120, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
IMX8ULP_PAD_PTC9__FLEXSPI0_A_DATA1 = IOMUX_PAD(0x0124, 0x0124, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
IMX8ULP_PAD_PTC10__FLEXSPI0_A_DATA0 = IOMUX_PAD(0x0128, 0x0128, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+ IMX8ULP_PAD_PTC10__PTC10 = IOMUX_PAD(0x0128, 0x0128, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
IMX8ULP_PAD_PTD0__SDHC0_RESET_b = IOMUX_PAD(0x0000, 0x0000, 0x8, 0x0000, 0x0, 0),
diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
deleted file mode 100644
index b3e6b3fa45..0000000000
--- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2021 NXP
- */
-
-#ifndef __S400_API_H__
-#define __S400_API_H__
-
-#define AHAB_VERSION 0x6
-#define AHAB_CMD_TAG 0x17
-#define AHAB_RESP_TAG 0xe1
-
-#define AHAB_LOG_CID 0x21
-#define AHAB_AUTH_OEM_CTNR_CID 0x87
-#define AHAB_VERIFY_IMG_CID 0x88
-#define AHAB_RELEASE_CTNR_CID 0x89
-#define AHAB_WRITE_SECURE_FUSE_REQ_CID 0x91
-#define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95
-#define AHAB_READ_FUSE_REQ_CID 0x97
-#define AHAB_GET_FW_VERSION_CID 0x9D
-#define AHAB_RELEASE_RDC_REQ_CID 0xC4
-#define AHAB_WRITE_FUSE_REQ_CID 0xD6
-#define AHAB_CAAM_RELEASE_CID 0xD7
-
-#define S400_MAX_MSG 255U
-
-struct imx8ulp_s400_msg {
- u8 version;
- u8 size;
- u8 command;
- u8 tag;
- u32 data[(S400_MAX_MSG - 1U)];
-};
-
-int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response);
-int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
-int ahab_release_container(u32 *response);
-int ahab_verify_image(u32 img_id, u32 *response);
-int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
-int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
-int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response);
-int ahab_release_caam(u32 core_did, u32 *response);
-int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
-int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
-
-#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 5f030eaa0a..e240ee6fca 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -19,5 +19,6 @@ enum boot_device get_boot_device(void);
void set_lpav_qos(void);
void load_lposc_fuse(void);
bool m33_image_booted(void);
+bool is_m33_handshake_necessary(void);
int m33_image_handshake(ulong timeout_ms);
#endif
diff --git a/arch/arm/include/asm/arch-imx9/ccm_regs.h b/arch/arm/include/asm/arch-imx9/ccm_regs.h
new file mode 100644
index 0000000000..d326a6ea51
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/ccm_regs.h
@@ -0,0 +1,266 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_CCM_REGS_H__
+#define __ASM_ARCH_IMX9_CCM_REGS_H__
+#define IMX93_CLK_ROOT_MAX 95
+#define IMX93_CLK_CCGR_MAX 127
+
+#define ARM_A55_PERIPH_CLK_ROOT 0
+#define ARM_A55_MTR_BUS_CLK_ROOT 1
+#define ARM_A55_CLK_ROOT 2
+#define M33_CLK_ROOT 3
+#define SENTINEL_CLK_ROOT 4
+#define BUS_WAKEUP_CLK_ROOT 5
+#define BUS_AON_CLK_ROOT 6
+#define WAKEUP_AXI_CLK_ROOT 7
+#define SWO_TRACE_CLK_ROOT 8
+#define M33_SYSTICK_CLK_ROOT 9
+#define FLEXIO1_CLK_ROOT 10
+#define FLEXIO2_CLK_ROOT 11
+#define LPIT1_CLK_ROOT 12
+#define LPIT2_CLK_ROOT 13
+#define LPTMR1_CLK_ROOT 14
+#define LPTMR2_CLK_ROOT 15
+#define TPM1_CLK_ROOT 16
+#define TPM2_CLK_ROOT 17
+#define TPM3_CLK_ROOT 18
+#define TPM4_CLK_ROOT 19
+#define TPM5_CLK_ROOT 20
+#define TPM6_CLK_ROOT 21
+#define FLEXSPI1_CLK_ROOT 22
+#define CAN1_CLK_ROOT 23
+#define CAN2_CLK_ROOT 24
+#define LPUART1_CLK_ROOT 25
+#define LPUART2_CLK_ROOT 26
+#define LPUART3_CLK_ROOT 27
+#define LPUART4_CLK_ROOT 28
+#define LPUART5_CLK_ROOT 29
+#define LPUART6_CLK_ROOT 30
+#define LPUART7_CLK_ROOT 31
+#define LPUART8_CLK_ROOT 32
+#define LPI2C1_CLK_ROOT 33
+#define LPI2C2_CLK_ROOT 34
+#define LPI2C3_CLK_ROOT 35
+#define LPI2C4_CLK_ROOT 36
+#define LPI2C5_CLK_ROOT 37
+#define LPI2C6_CLK_ROOT 38
+#define LPI2C7_CLK_ROOT 39
+#define LPI2C8_CLK_ROOT 40
+#define LPSPI1_CLK_ROOT 41
+#define LPSPI2_CLK_ROOT 42
+#define LPSPI3_CLK_ROOT 43
+#define LPSPI4_CLK_ROOT 44
+#define LPSPI5_CLK_ROOT 45
+#define LPSPI6_CLK_ROOT 46
+#define LPSPI7_CLK_ROOT 47
+#define LPSPI8_CLK_ROOT 48
+#define I3C1_CLK_ROOT 49
+#define I3C2_CLK_ROOT 50
+#define USDHC1_CLK_ROOT 51
+#define USDHC2_CLK_ROOT 52
+#define USDHC3_CLK_ROOT 53
+#define SAI1_CLK_ROOT 54
+#define SAI2_CLK_ROOT 55
+#define SAI3_CLK_ROOT 56
+#define CCM_CKO1_CLK_ROOT 57
+#define CCM_CKO2_CLK_ROOT 58
+#define CCM_CKO3_CLK_ROOT 59
+#define CCM_CKO4_CLK_ROOT 60
+#define HSIO_CLK_ROOT 61
+#define HSIO_USB_TEST_60M_CLK_ROOT 62
+#define HSIO_ACSCAN_80M_CLK_ROOT 63
+#define HSIO_ACSCAN_480M_CLK_ROOT 64
+#define NIC_CLK_ROOT 65
+#define NIC_APB_CLK_ROOT 66
+#define ML_APB_CLK_ROOT 67
+#define ML_CLK_ROOT 68
+#define MEDIA_AXI_CLK_ROOT 69
+#define MEDIA_APB_CLK_ROOT 70
+#define MEDIA_LDB_CLK_ROOT 71
+#define MEDIA_DISP_PIX_CLK_ROOT 72
+#define CAM_PIX_CLK_ROOT 73
+#define MIPI_TEST_BYTE_CLK_ROOT 74
+#define MIPI_PHY_CFG_CLK_ROOT 75
+#define DRAM_ALT_CLK_ROOT 76
+#define DRAM_APB_CLK_ROOT 77
+#define ADC_CLK_ROOT 78
+#define PDM_CLK_ROOT 79
+#define TSTMR1_CLK_ROOT 80
+#define TSTMR2_CLK_ROOT 81
+#define MQS1_CLK_ROOT 82
+#define MQS2_CLK_ROOT 83
+#define AUDIO_XCVR_CLK_ROOT 84
+#define SPDIF_CLK_ROOT 85
+#define ENET_CLK_ROOT 86
+#define ENET_TIMER1_CLK_ROOT 87
+#define ENET_TIMER2_CLK_ROOT 88
+#define ENET_REF_CLK_ROOT 89
+#define ENET_REF_PHY_CLK_ROOT 90
+#define I3C1_SLOW_CLK_ROOT 91
+#define I3C2_SLOW_CLK_ROOT 92
+#define USB_PHY_BURUNIN_CLK_ROOT 93
+#define PAL_CAME_SCAN_CLK_ROOT 94
+#define CLK_ROOT_NUM 95
+
+#define CCGR_A55 0
+#define CCGR_CM33 1
+#define CCGR_ARMTROUT 2
+#define CCGR_SENT 3
+#define CCGR_BUSM 4
+#define CCGR_BUS7 5
+#define CCGR_BUSD 6
+#define CCGR_ANAD 7
+#define CCGR_SRC 8
+#define CCGR_CCM 9
+#define CCGR_GPC 10
+#define CCGR_ADC 11
+#define CCGR_WDG1 12
+#define CCGR_WDG2 13
+#define CCGR_WDG3 14
+#define CCGR_WDG4 15
+#define CCGR_WDG5 16
+#define CCGR_SEM1 17
+#define CCGR_SEM2 18
+#define CCGR_MUA 19
+#define CCGR_MUB 20
+#define CCGR_DMA1 21
+#define CCGR_DMA2 22
+#define CCGR_ROMCA55 23
+#define CCGR_ROMCM33 24
+#define CCGR_QSP1 25
+#define CCGR_AONRDC 26
+#define CCGR_WKUPRDC 27
+#define CCGR_FUSE 28
+#define CCGR_SNVH 29
+#define CCGR_SNVS 30
+#define CCGR_TRAC 31
+#define CCGR_SWO 32
+#define CCGR_IOCG 33
+#define CCGR_PIO1 34
+#define CCGR_PIO2 35
+#define CCGR_PIO3 36
+#define CCGR_PIO4 37
+#define CCGR_FIO1 38
+#define CCGR_FIO2 39
+#define CCGR_PIT1 40
+#define CCGR_PIT2 41
+#define CCGR_GPT1 42
+#define CCGR_GPT2 43
+#define CCGR_TPM1 44
+#define CCGR_TPM2 45
+#define CCGR_TPM3 46
+#define CCGR_TPM4 47
+#define CCGR_TPM5 48
+#define CCGR_TPM6 49
+#define CCGR_CAN1 50
+#define CCGR_CAN2 51
+#define CCGR_URT1 52
+#define CCGR_URT2 53
+#define CCGR_URT3 54
+#define CCGR_URT4 55
+#define CCGR_URT5 56
+#define CCGR_URT6 57
+#define CCGR_URT7 58
+#define CCGR_URT8 59
+#define CCGR_I2C1 60
+#define CCGR_I2C2 61
+#define CCGR_I2C3 62
+#define CCGR_I2C4 63
+#define CCGR_I2C5 64
+#define CCGR_I2C6 65
+#define CCGR_I2C7 66
+#define CCGR_I2C8 67
+#define CCGR_SPI1 68
+#define CCGR_SPI2 69
+#define CCGR_SPI3 70
+#define CCGR_SPI4 71
+#define CCGR_SPI5 72
+#define CCGR_SPI6 73
+#define CCGR_SPI7 74
+#define CCGR_SPI8 75
+#define CCGR_I3C1 76
+#define CCGR_I3C2 77
+#define CCGR_USDHC1 78
+#define CCGR_USDHC2 79
+#define CCGR_USDHC3 80
+#define CCGR_SAI1 81
+#define CCGR_SAI2 82
+#define CCGR_SAI3 83
+#define CCGR_W2AO 84
+#define CCGR_AO2W 85
+#define CCGR_MIPIC 86
+#define CCGR_MIPID 87
+#define CCGR_LVDS 88
+#define CCGR_LCDIF 89
+#define CCGR_PXP 90
+#define CCGR_ISI 91
+#define CCGR_NMED 92
+#define CCGR_DFI 93
+#define CCGR_DDRC 94
+#define CCGR_DFIC 95
+#define CCGR_DSSI 96
+#define CCGR_DBYP 97
+#define CCGR_DAPB 98
+#define CCGR_DRAMP 99
+#define CCGR_DCLKC 100
+#define CCGR_NCTL 101
+#define CCGR_GIC 102
+#define CCGR_NICAPB 103
+#define CCGR_USBC 104
+#define CCGR_USBT 105
+#define CCGR_HSIO 106
+#define CCGR_PDM 107
+#define CCGR_MQS1 108
+#define CCGR_MQS2 109
+#define CCGR_AXCVR 110
+#define CCGR_MECC 111
+#define CCGR_SPDIF 112
+#define CCGR_ML2NIC 113
+#define CCGR_MED2NIC 114
+#define CCGR_HSIO2NIC 115
+#define CCGR_W2NIC 116
+#define CCGR_NIC2W 117
+#define CCGR_NIC2DDR 118
+#define CCGR_HSIO32K 119
+#define CCGR_ENET1 120
+#define CCGR_ENETQOS 121
+#define CCGR_SYSCNT 122
+#define CCGR_TSTMR1 123
+#define CCGR_TSTMR2 124
+#define CCGR_TMC 125
+#define CCGR_PMRO 126
+#define CCGR_NUM 127
+
+#define SHARED_GPR_EXT_CLK 0
+#define SHARED_GPR_EXT_CLK_SEL_EXT1 0
+#define SHARED_GPR_EXT_CLK_SEL_EXT2 BIT(0)
+#define SHARED_GPR_EXT_CLK_SEL_EXT3 BIT(1)
+#define SHARED_GPR_EXT_CLK_SEL_EXT4 GENMASK(1, 0)
+
+#define SHARED_GPR_A55_CLK 1
+#define SHARED_GPR_A55_CLK_SEL_CCM 0
+#define SHARED_GPR_A55_CLK_SEL_PLL BIT(0)
+
+#define SHARED_GPR_DRAM_CLK 2
+#define SHARED_GPR_DRAM_CLK_SEL_PLL 0
+#define SHARED_GPR_DRAM_CLK_SEL_CCM BIT(0)
+
+#define SHARED_GPR_NUM 8
+#define PRIVATE_GPR_NUM 8
+
+#define CLK_ROOT_STATUS_OFF BIT(24)
+#define CLK_ROOT_STATUS_CHANGING BIT(31)
+#define CLK_ROOT_MUX_MASK GENMASK(9, 8)
+#define CLK_ROOT_MUX_SHIFT 8
+#define CLK_ROOT_DIV_MASK GENMASK(7, 0)
+
+#define CCM_AUTHEN_LOCK_TZ BIT(11)
+#define CCM_AUTHEN_TZ_NS BIT(9)
+#define CCM_AUTHEN_TZ_USER BIT(8)
+#define CCM_AUTHEN_CPULPM_MODE BIT(2)
+#define CCM_AUTHEN_AUTO_CTRL BIT(3)
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h
new file mode 100644
index 0000000000..5cb762d429
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -0,0 +1,249 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ *
+ * Peng Fan <peng.fan at nxp.com>
+ */
+
+#ifndef __CLOCK_IMX9__
+#define __CLOCK_IMX9__
+
+#include <linux/bitops.h>
+
+#define MHZ(x) ((x) * 1000000UL)
+
+enum enet_freq {
+ ENET_25MHZ = 0,
+ ENET_50MHZ,
+ ENET_125MHZ,
+};
+
+enum ccm_clk_src {
+ OSC_24M_CLK,
+ ARM_PLL,
+ ARM_PLL_CLK,
+ SYS_PLL_PG,
+ SYS_PLL_PFD0_PG,
+ SYS_PLL_PFD0,
+ SYS_PLL_PFD0_DIV2,
+ SYS_PLL_PFD1_PG,
+ SYS_PLL_PFD1,
+ SYS_PLL_PFD1_DIV2,
+ SYS_PLL_PFD2_PG,
+ SYS_PLL_PFD2,
+ SYS_PLL_PFD2_DIV2,
+ AUDIO_PLL,
+ AUDIO_PLL_CLK,
+ DRAM_PLL,
+ DRAM_PLL_CLK,
+ VIDEO_PLL,
+ VIDEO_PLL_CLK,
+ OSCPLL_END,
+ EXT_CLK,
+};
+
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_IPG_CLK,
+ MXC_FLEXSPI_CLK,
+ MXC_CSPI_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_UART_CLK,
+ MXC_I2C_CLK,
+ MXC_FEC_CLK,
+};
+
+struct ccm_obs {
+ u32 direct;
+ u32 reserved[31];
+};
+
+struct ccm_gpr {
+ u32 gpr;
+ u32 gpr_set;
+ u32 gpr_clr;
+ u32 gpr_tog;
+ u32 authen;
+ u32 authen_set;
+ u32 authen_clr;
+ u32 authen_tog;
+};
+
+struct ccm_lpcg_oscpll {
+ u32 direct;
+ u32 lpm_status0;
+ u32 lpm_status1;
+ u32 reserved0;
+ u32 lpm0;
+ u32 lpm1;
+ u32 reserved1;
+ u32 lpm_cur;
+ u32 status0;
+ u32 status1;
+ u32 reserved2[2];
+ u32 authen;
+ u32 reserved3[3];
+};
+
+struct ccm_root {
+ u32 control;
+ u32 control_set;
+ u32 control_clr;
+ u32 control_tog;
+ u32 reserved[4];
+ u32 status0;
+ u32 reserved1[3];
+ u32 authen;
+ u32 reserved2[19];
+};
+
+struct ccm_reg {
+ struct ccm_root clk_roots[95]; /* 0x0 */
+ u32 reserved_0[1312];
+ struct ccm_obs clk_obs[6]; /* 0x4400 */
+ u32 reserved_1[64];
+ struct ccm_gpr clk_shared_gpr[8]; /* 0x4800 */
+ u32 reserved_2[192];
+ struct ccm_gpr clk_private_gpr[8]; /* 0x4C00 */
+ u32 reserved_3[192];
+ struct ccm_lpcg_oscpll clk_oscplls[19]; /* 0x5000 */
+ u32 reserved_4[2768];
+ struct ccm_lpcg_oscpll clk_lpcgs[122]; /* 0x8000 */
+};
+
+struct ana_pll_reg_elem {
+ u32 reg;
+ u32 reg_set;
+ u32 reg_clr;
+ u32 reg_tog;
+};
+
+struct ana_pll_dfs {
+ struct ana_pll_reg_elem dfs_ctrl;
+ struct ana_pll_reg_elem dfs_div;
+};
+
+struct ana_pll_reg {
+ struct ana_pll_reg_elem ctrl;
+ struct ana_pll_reg_elem ana_prg;
+ struct ana_pll_reg_elem test;
+ struct ana_pll_reg_elem ss; /* Spread spectrum */
+ struct ana_pll_reg_elem num; /* numerator */
+ struct ana_pll_reg_elem denom; /* demoninator */
+ struct ana_pll_reg_elem div;
+ struct ana_pll_dfs dfs[4];
+ u32 pll_status;
+ u32 dfs_status;
+ u32 reserved[2];
+};
+
+struct anatop_reg {
+ u32 osc_ctrl;
+ u32 osc_state;
+ u32 reserved_0[510];
+ u32 chip_version;
+ u32 reserved_1[511];
+ struct ana_pll_reg arm_pll;
+ struct ana_pll_reg sys_pll;
+ struct ana_pll_reg audio_pll;
+ struct ana_pll_reg dram_pll;
+ struct ana_pll_reg video_pll;
+};
+
+#define PLL_CTRL_HW_CTRL_SEL BIT(16)
+#define PLL_CTRL_CLKMUX_BYPASS BIT(2)
+#define PLL_CTRL_CLKMUX_EN BIT(1)
+#define PLL_CTRL_POWERUP BIT(0)
+
+#define PLL_STATUS_PLL_LOCK BIT(0)
+#define PLL_DFS_CTRL_ENABLE BIT(31)
+#define PLL_DFS_CTRL_CLKOUT BIT(30)
+#define PLL_DFS_CTRL_CLKOUT_DIV2 BIT(29)
+#define PLL_DFS_CTRL_BYPASS BIT(23)
+
+#define PLL_SS_EN BIT(15)
+
+struct imx_intpll_rate_table {
+ u32 rate; /*khz*/
+ int rdiv;
+ int mfi;
+ int odiv;
+};
+
+struct imx_fracpll_rate_table {
+ u32 rate; /*khz*/
+ int rdiv;
+ int mfi;
+ int odiv;
+ int mfn;
+ int mfd;
+};
+
+#define INT_PLL_RATE(_rate, _r, _m, _o) \
+ { \
+ .rate = (_rate), \
+ .rdiv = (_r), \
+ .mfi = (_m), \
+ .odiv = (_o), \
+ }
+
+#define FRAC_PLL_RATE(_rate, _r, _m, _o, _n, _d) \
+ { \
+ .rate = (_rate), \
+ .rdiv = (_r), \
+ .mfi = (_m), \
+ .odiv = (_o), \
+ .mfn = (_n), \
+ .mfd = (_d), \
+ }
+
+struct clk_root_map {
+ u32 clk_root_id;
+ u32 mux_type;
+};
+
+
+int clock_init(void);
+u32 get_clk_src_rate(enum ccm_clk_src source);
+u32 get_lpuart_clk(void);
+void init_uart_clk(u32 index);
+void init_clk_usdhc(u32 index);
+int enable_i2c_clk(unsigned char enable, u32 i2c_num);
+u32 imx_get_i2cclk(u32 i2c_num);
+u32 mxc_get_clock(enum mxc_clock clk);
+void dram_pll_init(ulong pll_val);
+void dram_enable_bypass(ulong clk_val);
+void dram_disable_bypass(void);
+
+int configure_intpll(enum ccm_clk_src pll, u32 freq);
+
+int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable);
+int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable);
+int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable);
+int ccm_clk_src_config_lpm(enum ccm_clk_src oscpll, u32 domain, u32 lpm_val);
+bool ccm_clk_src_is_clk_on(enum ccm_clk_src oscpll);
+int ccm_clk_src_tz_access(enum ccm_clk_src oscpll,
+ bool non_secure, bool user_mode, bool lock_tz);
+int ccm_clk_root_cfg(u32 clk_root_id, enum ccm_clk_src src, u32 div);
+u32 ccm_clk_root_get_rate(u32 clk_root_id);
+int ccm_clk_root_tz_access(u32 clk_root_id,
+ bool non_secure, bool user_mode, bool lock_tz);
+int ccm_lpcg_on(u32 lpcg, bool enable);
+int ccm_lpcg_lpm(u32 lpcg, bool enable);
+int ccm_lpcg_config_lpm(u32 lpcg, u32 domain, u32 lpm_val);
+bool ccm_lpcg_is_clk_on(u32 lpcg);
+int ccm_lpcg_tz_access(u32 lpcg,
+ bool non_secure, bool user_mode, bool lock_tz);
+int ccm_shared_gpr_set(u32 gpr, u32 val);
+int ccm_shared_gpr_get(u32 gpr, u32 *val);
+int ccm_shared_gpr_tz_access(u32 gpr,
+ bool non_secure, bool user_mode, bool lock_tz);
+
+void enable_usboh3_clk(unsigned char enable);
+int set_clk_enet(enum enet_freq type);
+int set_clk_eqos(enum enet_freq type);
+void mxs_set_lcdclk(u32 base_addr, u32 freq);
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h
new file mode 100644
index 0000000000..83983ed391
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/ddr.h
@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8M_DDR_H
+#define __ASM_ARCH_IMX8M_DDR_H
+
+#include <asm/io.h>
+#include <asm/types.h>
+
+#define DDR_CTL_BASE 0x4E300000
+#define DDR_PHY_BASE 0x4E100000
+#define DDRMIX_BLK_CTRL_BASE 0x4E010000
+
+#define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24)
+#define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104)
+#define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110)
+#define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160)
+#define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48)
+
+#define SRC_BASE_ADDR (0x44460000)
+#define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400)
+#define REG_SRC_DPHY_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x20)
+#define REG_SRC_DPHY_SINGLE_RESET_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x24)
+
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (DDR_PHY_BASE + (X * 0x2000000))
+#define DDRPHY_MEM(X) (DDR_PHY_BASE + (X * 0x2000000) + 0x50000)
+
+/* PHY State */
+enum pstate {
+ PS0,
+ PS1,
+ PS2,
+ PS3,
+};
+
+enum msg_response {
+ TRAIN_SUCCESS = 0x7,
+ TRAIN_STREAM_START = 0x8,
+ TRAIN_FAIL = 0xff,
+};
+
+/* user data type */
+enum fw_type {
+ FW_1D_IMAGE,
+ FW_2D_IMAGE,
+};
+
+struct dram_cfg_param {
+ unsigned int reg;
+ unsigned int val;
+};
+
+struct dram_fsp_msg {
+ unsigned int drate;
+ enum fw_type fw_type;
+ struct dram_cfg_param *fsp_cfg;
+ unsigned int fsp_cfg_num;
+};
+
+struct dram_timing_info {
+ /* umctl2 config */
+ struct dram_cfg_param *ddrc_cfg;
+ unsigned int ddrc_cfg_num;
+ /* ddrphy config */
+ struct dram_cfg_param *ddrphy_cfg;
+ unsigned int ddrphy_cfg_num;
+ /* ddr fsp train info */
+ struct dram_fsp_msg *fsp_msg;
+ unsigned int fsp_msg_num;
+ /* ddr phy trained CSR */
+ struct dram_cfg_param *ddrphy_trained_csr;
+ unsigned int ddrphy_trained_csr_num;
+ /* ddr phy PIE */
+ struct dram_cfg_param *ddrphy_pie;
+ unsigned int ddrphy_pie_num;
+ /* initialized drate table */
+ unsigned int fsp_table[4];
+};
+
+extern struct dram_timing_info dram_timing;
+
+void ddr_load_train_firmware(enum fw_type type);
+int ddr_init(struct dram_timing_info *timing_info);
+int ddr_cfg_phy(struct dram_timing_info *timing_info);
+void load_lpddr4_phy_pie(void);
+void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
+void dram_config_save(struct dram_timing_info *info, unsigned long base);
+void board_dram_ecc_scrub(void);
+void ddrc_inline_ecc_scrub(unsigned int start_address,
+ unsigned int range_address);
+void ddrc_inline_ecc_scrub_end(unsigned int start_address,
+ unsigned int range_address);
+
+/* utils function for ddr phy training */
+int wait_ddrphy_training_complete(void);
+void ddrphy_init_set_dfi_clk(unsigned int drate);
+void ddrphy_init_read_msg_block(enum fw_type type);
+
+void get_trained_CDD(unsigned int fsp);
+
+ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr);
+
+static inline void reg32_write(unsigned long addr, u32 val)
+{
+ writel(val, addr);
+}
+
+static inline u32 reg32_read(unsigned long addr)
+{
+ return readl(addr);
+}
+
+static inline void reg32setbit(unsigned long addr, u32 bit)
+{
+ setbits_le32(addr, (1 << bit));
+}
+
+#define dwc_ddrphy_apb_wr(addr, data) \
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data)
+#define dwc_ddrphy_apb_rd(addr) \
+ reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
+
+extern struct dram_cfg_param ddrphy_trained_csr[];
+extern uint32_t ddrphy_trained_csr_num;
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/gpio.h b/arch/arm/include/asm/arch-imx9/gpio.h
new file mode 100644
index 0000000000..599f7511c3
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/gpio.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_GPIO_H
+#define __ASM_ARCH_IMX9_GPIO_H
+
+#include <common.h>
+
+struct gpio_regs {
+ u32 gpio_pdor;
+ u32 gpio_psor;
+ u32 gpio_pcor;
+ u32 gpio_ptor;
+ u32 gpio_pdir;
+ u32 gpio_pddr;
+ u32 gpio_pidr;
+ u8 gpio_pxdr[32];
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
new file mode 100644
index 0000000000..593409c30c
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_REGS_H__
+#define __ASM_ARCH_IMX9_REGS_H__
+
+#define ARCH_MXC
+#define FEC_QUIRK_ENET_MAC
+
+#define IOMUXC_BASE_ADDR 0x443C0000UL
+#define CCM_BASE_ADDR 0x44450000UL
+#define CCM_CCGR_BASE_ADDR 0x44458000UL
+#define SYSCNT_CTRL_BASE_ADDR 0x44290000
+
+#define WDG3_BASE_ADDR 0x42490000UL
+#define WDG4_BASE_ADDR 0x424a0000UL
+#define WDG5_BASE_ADDR 0x424b0000UL
+
+#define ANATOP_BASE_ADDR 0x44480000UL
+
+#define USB1_BASE_ADDR 0x4c100000
+#define USB2_BASE_ADDR 0x4c200000
+
+#define USB_BASE_ADDR USB1_BASE_ADDR
+
+#define FSB_BASE_ADDR 0x47510000
+
+#define BLK_CTRL_WAKEUPMIX_BASE_ADDR 0x42420000
+#define BLK_CTRL_S_ANOMIX_BASE_ADDR 0x444f0000
+
+#define SRC_IPS_BASE_ADDR (0x44460000)
+#define SRC_GLOBAL_RBASE (SRC_IPS_BASE_ADDR + 0x0000)
+
+#define SRC_DDR_RBASE (SRC_IPS_BASE_ADDR + 0x1000)
+#define SRC_ML_RBASE (SRC_IPS_BASE_ADDR + 0x1800)
+#define SRC_MEDIA_RBASE (SRC_IPS_BASE_ADDR + 0x2400)
+#define SRC_M33P_RBASE (SRC_IPS_BASE_ADDR + 0x2800)
+
+#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT BIT(0)
+#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT BIT(2)
+#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
+#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
+
+#define IMG_CONTAINER_BASE (0x80000000UL)
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#include <stdbool.h>
+
+#define BCTRL_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
+#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0)
+
+#define BCTRL_S_ANOMIX_M33_CPU_WAIT_MASK BIT(2)
+
+enum mix_power_domain {
+ MIX_PD_MEDIAMIX,
+ MIX_PD_MLMIX,
+ MIX_PD_DDRMIX,
+};
+
+enum src_mix_slice_id {
+ SRC_MIX_EDGELOCK = 0,
+ SRC_MIX_AONMIX = 1,
+ SRC_MIX_WAKEUPMIX = 2,
+ SRC_MIX_DDRMIX = 3,
+ SRC_MIX_DDRPHY = 4,
+ SRC_MIX_ML = 5,
+ SRC_MIX_NIC = 6,
+ SRC_MIX_HSIO = 7,
+ SRC_MIX_MEDIA = 8,
+ SRC_MIX_CM33 = 9,
+ SRC_MIX_CA55C0 = 10,
+ SRC_MIX_CA55C1 = 11,
+ SRC_MIX_CA55CLUSTER = 12,
+};
+
+enum src_mem_slice_id {
+ SRC_MEM_AONMIX = 0,
+ SRC_MEM_WAKEUPMIX = 1,
+ SRC_MEM_DDRMIX = 2,
+ SRC_MEM_DDRPHY = 3,
+ SRC_MEM_ML = 4,
+ SRC_MEM_NIC = 5,
+ SRC_MEM_OCRAM = 6,
+ SRC_MEM_HSIO = 7,
+ SRC_MEM_MEDIA = 8,
+ SRC_MEM_CA55C0 = 9,
+ SRC_MEM_CA55C1 = 10,
+ SRC_MEM_CA55CLUSTER = 11,
+ SRC_MEM_L3 = 12,
+};
+
+struct blk_ctrl_s_aonmix_regs {
+ u32 cm33_irq_mask[7];
+ u32 initnsvtor;
+ u32 reserved1[8];
+ u32 ca55_irq_mask[7];
+ u32 initsvtor;
+ u32 m33_cfg;
+ u32 reserved2[11];
+ u32 axbs_aon_ctrl;
+ u32 reserved3[27];
+ u32 dap_access_stkybit;
+ u32 reserved4[3];
+ u32 lp_handshake[2];
+ u32 ca55_cpuwait;
+ u32 ca55_rvbaraddr0_l;
+ u32 ca55_rvbaraddr0_h;
+ u32 ca55_rvbaraddr1_l;
+ u32 ca55_rvbaraddr1_h;
+ u32 s401_irq_mask;
+ u32 s401_reset_req_mask;
+ u32 s401_halt_st;
+ u32 ca55_mode;
+ u32 nmi_mask;
+ u32 nmi_clr;
+ u32 wdog_any_mask;
+ u32 s4v1_ipi_noclk_ref1;
+};
+
+struct blk_ctrl_wakeupmix_regs {
+ u32 upper_addr;
+ u32 ipg_debug_cm33;
+ u32 reserved[2];
+ u32 qch_dis;
+ u32 ssi;
+ u32 reserved1[1];
+ u32 dexsc_err;
+ u32 mqs_setting;
+ u32 sai_clk_sel;
+ u32 eqos_gpr;
+ u32 enet_clk_sel;
+ u32 reserved2[1];
+ u32 volt_detect;
+ u32 i3c2_wakeup;
+ u32 ipg_debug_ca55c0;
+ u32 ipg_debug_ca55c1;
+ u32 axi_attr_cfg;
+ u32 i3c2_sda_irq;
+};
+
+struct mu_type {
+ u32 ver;
+ u32 par;
+ u32 cr;
+ u32 sr;
+ u32 reserved0[60];
+ u32 fcr;
+ u32 fsr;
+ u32 reserved1[2];
+ u32 gier;
+ u32 gcr;
+ u32 gsr;
+ u32 reserved2;
+ u32 tcr;
+ u32 tsr;
+ u32 rcr;
+ u32 rsr;
+ u32 reserved3[52];
+ u32 tr[16];
+ u32 reserved4[16];
+ u32 rr[16];
+ u32 reserved5[14];
+ u32 mu_attr;
+};
+
+struct src_general_regs {
+ u32 reserved[1];
+ u32 authen_ctrl;
+ u32 reserved1[2];
+ u32 scr;
+ u32 srtmr;
+ u32 srmask;
+ u32 reserved2[1];
+ u32 srmr[6];
+ u32 reserved3[2];
+ u32 sbmr[2];
+ u32 reserved4[2];
+ u32 srsr;
+ u32 gpr[19];
+ u32 reserved5[24];
+ u32 gpr20;
+ u32 cm_quiesce;
+ u32 cold_reset_ssar_ack_ctrl;
+ u32 sp_iso_ctrl;
+ u32 rom_lp_ctrl;
+ u32 a55_deny_stat;
+};
+
+struct src_mem_slice_regs {
+ u32 reserved[1];
+ u32 mem_ctrl;
+ u32 memlp_ctrl_0;
+ u32 reserved1[1];
+ u32 memlp_ctrl_1;
+ u32 memlp_ctrl_2;
+ u32 mem_stat;
+};
+
+struct src_mix_slice_regs {
+ u32 reserved[1];
+ u32 authen_ctrl;
+ u32 reserved1[2];
+ u32 lpm_setting[3];
+ u32 reserved2[1];
+ u32 slice_sw_ctrl;
+ u32 single_reset_sw_ctrl;
+ u32 reserved3[6];
+ u32 a55_hdsk_ack_ctrl;
+ u32 a55_hdsk_ack_stat;
+ u32 reserved4[2];
+ u32 ssar_ack_ctrl;
+ u32 ssar_ack_stat;
+ u32 reserved5[1];
+ u32 iso_off_dly_por;
+ u32 iso_on_dly;
+ u32 iso_off_dly;
+ u32 psw_off_lf_dly;
+ u32 reserved6[1];
+ u32 psw_off_hf_dly;
+ u32 psw_on_lf_dly;
+ u32 psw_on_hf_dly;
+ u32 reserved7[1];
+ u32 psw_ack_ctrl[2];
+ u32 psw_ack_stat;
+ u32 reserved8[1];
+ u32 mtr_ack_ctrl;
+ u32 mtr_ack_stat;
+ u32 reserved9[2];
+ u32 upi_stat[4];
+ u32 fsm_stat;
+ u32 func_stat;
+};
+
+bool is_usb_boot(void);
+void disconnect_from_pc(void);
+#define is_boot_from_usb is_usb_boot
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/imx93_pins.h b/arch/arm/include/asm/arch-imx9/imx93_pins.h
new file mode 100644
index 0000000000..ae0eaa8354
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/imx93_pins.h
@@ -0,0 +1,729 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX93_PINS_H__
+#define __ASM_ARCH_IMX93_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+ MX93_PAD_DAP_TDI__JTAG_MUX_TDI = IOMUX_PAD(0x01B0, 0x0000, 0, 0x03D8, 0, 0),
+ MX93_PAD_DAP_TDI__MQS2_LEFT = IOMUX_PAD(0x01B0, 0x0000, 1, 0x0000, 0, 0),
+ MX93_PAD_DAP_TDI__CAN2_TX = IOMUX_PAD(0x01B0, 0x0000, 3, 0x0000, 0, 0),
+ MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 = IOMUX_PAD(0x01B0, 0x0000, 4, 0x0000, 0, 0),
+ MX93_PAD_DAP_TDI__GPIO3_IO28 = IOMUX_PAD(0x01B0, 0x0000, 5, 0x0000, 0, 0),
+ MX93_PAD_DAP_TDI__LPUART5_RX = IOMUX_PAD(0x01B0, 0x0000, 6, 0x0430, 0, 0),
+
+ MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS = IOMUX_PAD(0x01B4, 0x0004, 0, 0x03DC, 0, 0),
+ MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 = IOMUX_PAD(0x01B4, 0x0004, 4, 0x0000, 0, 0),
+ MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 = IOMUX_PAD(0x01B4, 0x0004, 5, 0x0000, 0, 0),
+ MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B = IOMUX_PAD(0x01B4, 0x0004, 6, 0x0000, 0, 0),
+
+ MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK = IOMUX_PAD(0x01B8, 0x0008, 0, 0x03D4, 0, 0),
+ MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 = IOMUX_PAD(0x01B8, 0x0008, 4, 0x0000, 0, 0),
+ MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 = IOMUX_PAD(0x01B8, 0x0008, 5, 0x0000, 0, 0),
+ MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B = IOMUX_PAD(0x01B8, 0x0008, 6, 0x042C, 0, 0),
+
+ MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO = IOMUX_PAD(0x01BC, 0x000C, 0, 0x0000, 0, 0),
+ MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT = IOMUX_PAD(0x01BC, 0x000C, 1, 0x0000, 0, 0),
+ MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX = IOMUX_PAD(0x01BC, 0x000C, 3, 0x0364, 0, 0),
+ MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 = IOMUX_PAD(0x01BC, 0x000C, 4, 0x0000, 0, 0),
+ MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 = IOMUX_PAD(0x01BC, 0x000C, 5, 0x0000, 0, 0),
+ MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX = IOMUX_PAD(0x01BC, 0x000C, 6, 0x0434, 0, 0),
+
+ MX93_PAD_GPIO_IO00__GPIO2_IO00 = IOMUX_PAD(0x01C0, 0x0010, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO00__LPI2C3_SDA = IOMUX_PAD(0x01C0, 0x0010, 1 | IOMUX_CONFIG_SION, 0x03E4, 0, 0),
+ MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK = IOMUX_PAD(0x01C0, 0x0010, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK = IOMUX_PAD(0x01C0, 0x0010, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO00__LPSPI6_PCS0 = IOMUX_PAD(0x01C0, 0x0010, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO00__LPUART5_TX = IOMUX_PAD(0x01C0, 0x0010, 5, 0x0434, 1, 0),
+ MX93_PAD_GPIO_IO00__LPI2C5_SDA = IOMUX_PAD(0x01C0, 0x0010, 6 | IOMUX_CONFIG_SION, 0x03EC, 0, 0),
+ MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 = IOMUX_PAD(0x01C0, 0x0010, 7, 0x036C, 0, 0),
+
+ MX93_PAD_GPIO_IO01__GPIO2_IO01 = IOMUX_PAD(0x01C4, 0x0014, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO01__LPI2C3_SCL = IOMUX_PAD(0x01C4, 0x0014, 1 | IOMUX_CONFIG_SION, 0x03E0, 0, 0),
+ MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 = IOMUX_PAD(0x01C4, 0x0014, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE = IOMUX_PAD(0x01C4, 0x0014, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO01__LPSPI6_SIN = IOMUX_PAD(0x01C4, 0x0014, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO01__LPUART5_RX = IOMUX_PAD(0x01C4, 0x0014, 5, 0x0430, 1, 0),
+ MX93_PAD_GPIO_IO01__LPI2C5_SCL = IOMUX_PAD(0x01C4, 0x0014, 6 | IOMUX_CONFIG_SION, 0x03E8, 0, 0),
+ MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 = IOMUX_PAD(0x01C4, 0x0014, 7, 0x0370, 0, 0),
+
+ MX93_PAD_GPIO_IO02__GPIO2_IO02 = IOMUX_PAD(0x01C8, 0x0018, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO02__LPI2C4_SDA = IOMUX_PAD(0x01C8, 0x0018, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC = IOMUX_PAD(0x01C8, 0x0018, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC = IOMUX_PAD(0x01C8, 0x0018, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO02__LPSPI6_SOUT = IOMUX_PAD(0x01C8, 0x0018, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO02__LPUART5_CTS_B = IOMUX_PAD(0x01C8, 0x0018, 5, 0x042C, 1, 0),
+ MX93_PAD_GPIO_IO02__LPI2C6_SDA = IOMUX_PAD(0x01C8, 0x0018, 6 | IOMUX_CONFIG_SION, 0x03F4, 0, 0),
+ MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 = IOMUX_PAD(0x01C8, 0x0018, 7, 0x0374, 0, 0),
+
+ MX93_PAD_GPIO_IO03__GPIO2_IO03 = IOMUX_PAD(0x01CC, 0x001C, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO03__LPI2C4_SCL = IOMUX_PAD(0x01CC, 0x001C, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC = IOMUX_PAD(0x01CC, 0x001C, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC = IOMUX_PAD(0x01CC, 0x001C, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO03__LPSPI6_SCK = IOMUX_PAD(0x01CC, 0x001C, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO03__LPUART5_RTS_B = IOMUX_PAD(0x01CC, 0x001C, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO03__LPI2C6_SCL = IOMUX_PAD(0x01CC, 0x001C, 6 | IOMUX_CONFIG_SION, 0x03F0, 0, 0),
+ MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 = IOMUX_PAD(0x01CC, 0x001C, 7, 0x0378, 0, 0),
+
+ MX93_PAD_GPIO_IO04__GPIO2_IO04 = IOMUX_PAD(0x01D0, 0x0020, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO04__TPM3_CH0 = IOMUX_PAD(0x01D0, 0x0020, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO04__PDM_CLK = IOMUX_PAD(0x01D0, 0x0020, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 = IOMUX_PAD(0x01D0, 0x0020, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO04__LPSPI7_PCS0 = IOMUX_PAD(0x01D0, 0x0020, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO04__LPUART6_TX = IOMUX_PAD(0x01D0, 0x0020, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO04__LPI2C6_SDA = IOMUX_PAD(0x01D0, 0x0020, 6 | IOMUX_CONFIG_SION, 0x03F4, 1, 0),
+ MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 = IOMUX_PAD(0x01D0, 0x0020, 7, 0x037C, 0, 0),
+
+ MX93_PAD_GPIO_IO05__GPIO2_IO05 = IOMUX_PAD(0x01D4, 0x0024, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO05__TPM4_CH0 = IOMUX_PAD(0x01D4, 0x0024, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 = IOMUX_PAD(0x01D4, 0x0024, 2, 0x0438, 0, 0),
+ MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 = IOMUX_PAD(0x01D4, 0x0024, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO05__LPSPI7_SIN = IOMUX_PAD(0x01D4, 0x0024, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO05__LPUART6_RX = IOMUX_PAD(0x01D4, 0x0024, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO05__LPI2C6_SCL = IOMUX_PAD(0x01D4, 0x0024, 6 | IOMUX_CONFIG_SION, 0x03F0, 1, 0),
+ MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 = IOMUX_PAD(0x01D4, 0x0024, 7, 0x0380, 0, 0),
+
+ MX93_PAD_GPIO_IO06__GPIO2_IO06 = IOMUX_PAD(0x01D8, 0x0028, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO06__TPM5_CH0 = IOMUX_PAD(0x01D8, 0x0028, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 = IOMUX_PAD(0x01D8, 0x0028, 2, 0x043C, 0, 0),
+ MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 = IOMUX_PAD(0x01D8, 0x0028, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO06__LPSPI7_SOUT = IOMUX_PAD(0x01D8, 0x0028, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO06__LPUART6_CTS_B = IOMUX_PAD(0x01D8, 0x0028, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO06__LPI2C7_SDA = IOMUX_PAD(0x01D8, 0x0028, 6 | IOMUX_CONFIG_SION, 0x03FC, 0, 0),
+ MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 = IOMUX_PAD(0x01D8, 0x0028, 7, 0x0384, 0, 0),
+
+ MX93_PAD_GPIO_IO07__GPIO2_IO07 = IOMUX_PAD(0x01DC, 0x002C, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO07__LPSPI3_PCS1 = IOMUX_PAD(0x01DC, 0x002C, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 = IOMUX_PAD(0x01DC, 0x002C, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 = IOMUX_PAD(0x01DC, 0x002C, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO07__LPSPI7_SCK = IOMUX_PAD(0x01DC, 0x002C, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO07__LPUART6_RTS_B = IOMUX_PAD(0x01DC, 0x002C, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO07__LPI2C7_SCL = IOMUX_PAD(0x01DC, 0x002C, 6 | IOMUX_CONFIG_SION, 0x03F8, 0, 0),
+ MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 = IOMUX_PAD(0x01DC, 0x002C, 7, 0x0388, 0, 0),
+
+ MX93_PAD_GPIO_IO08__GPIO2_IO08 = IOMUX_PAD(0x01E0, 0x0030, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO08__LPSPI3_PCS0 = IOMUX_PAD(0x01E0, 0x0030, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 = IOMUX_PAD(0x01E0, 0x0030, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 = IOMUX_PAD(0x01E0, 0x0030, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO08__TPM6_CH0 = IOMUX_PAD(0x01E0, 0x0030, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO08__LPUART7_TX = IOMUX_PAD(0x01E0, 0x0030, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO08__LPI2C7_SDA = IOMUX_PAD(0x01E0, 0x0030, 6 | IOMUX_CONFIG_SION, 0x03FC, 1, 0),
+ MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 = IOMUX_PAD(0x01E0, 0x0030, 7, 0x038C, 0, 0),
+
+ MX93_PAD_GPIO_IO09__GPIO2_IO09 = IOMUX_PAD(0x01E4, 0x0034, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO09__LPSPI3_SIN = IOMUX_PAD(0x01E4, 0x0034, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 = IOMUX_PAD(0x01E4, 0x0034, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 = IOMUX_PAD(0x01E4, 0x0034, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO09__TPM3_EXTCLK = IOMUX_PAD(0x01E4, 0x0034, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO09__LPUART7_RX = IOMUX_PAD(0x01E4, 0x0034, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO09__LPI2C7_SCL = IOMUX_PAD(0x01E4, 0x0034, 6 | IOMUX_CONFIG_SION, 0x03F8, 1, 0),
+ MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 = IOMUX_PAD(0x01E4, 0x0034, 7, 0x0390, 0, 0),
+
+ MX93_PAD_GPIO_IO10__GPIO2_IO10 = IOMUX_PAD(0x01E8, 0x0038, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO10__LPSPI3_SOUT = IOMUX_PAD(0x01E8, 0x0038, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 = IOMUX_PAD(0x01E8, 0x0038, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 = IOMUX_PAD(0x01E8, 0x0038, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO10__TPM4_EXTCLK = IOMUX_PAD(0x01E8, 0x0038, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO10__LPUART7_CTS_B = IOMUX_PAD(0x01E8, 0x0038, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO10__LPI2C8_SDA = IOMUX_PAD(0x01E8, 0x0038, 6 | IOMUX_CONFIG_SION, 0x0404, 0, 0),
+ MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 = IOMUX_PAD(0x01E8, 0x0038, 7, 0x0394, 0, 0),
+
+ MX93_PAD_GPIO_IO11__GPIO2_IO11 = IOMUX_PAD(0x01EC, 0x003C, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO11__LPSPI3_SCK = IOMUX_PAD(0x01EC, 0x003C, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 = IOMUX_PAD(0x01EC, 0x003C, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 = IOMUX_PAD(0x01EC, 0x003C, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO11__TPM5_EXTCLK = IOMUX_PAD(0x01EC, 0x003C, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO11__LPUART7_RTS_B = IOMUX_PAD(0x01EC, 0x003C, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO11__LPI2C8_SCL = IOMUX_PAD(0x01EC, 0x003C, 6 | IOMUX_CONFIG_SION, 0x0400, 0, 0),
+ MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 = IOMUX_PAD(0x01EC, 0x003C, 7, 0x0398, 0, 0),
+
+ MX93_PAD_GPIO_IO12__GPIO2_IO12 = IOMUX_PAD(0x01F0, 0x0040, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO12__TPM3_CH2 = IOMUX_PAD(0x01F0, 0x0040, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 = IOMUX_PAD(0x01F0, 0x0040, 2, 0x0440, 0, 0),
+ MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 = IOMUX_PAD(0x01F0, 0x0040, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO12__LPSPI8_PCS0 = IOMUX_PAD(0x01F0, 0x0040, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO12__LPUART8_TX = IOMUX_PAD(0x01F0, 0x0040, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO12__LPI2C8_SDA = IOMUX_PAD(0x01F0, 0x0040, 6 | IOMUX_CONFIG_SION, 0x0404, 1, 0),
+ MX93_PAD_GPIO_IO12__SAI3_RX_SYNC = IOMUX_PAD(0x01F0, 0x0040, 7, 0x0450, 0, 0),
+
+ MX93_PAD_GPIO_IO13__GPIO2_IO13 = IOMUX_PAD(0x01F4, 0x0044, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO13__TPM4_CH2 = IOMUX_PAD(0x01F4, 0x0044, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 = IOMUX_PAD(0x01F4, 0x0044, 2, 0x0444, 0, 0),
+ MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 = IOMUX_PAD(0x01F4, 0x0044, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO13__LPSPI8_SIN = IOMUX_PAD(0x01F4, 0x0044, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO13__LPUART8_RX = IOMUX_PAD(0x01F4, 0x0044, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO13__LPI2C8_SCL = IOMUX_PAD(0x01F4, 0x0044, 6 | IOMUX_CONFIG_SION, 0x0400, 1, 0),
+ MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 = IOMUX_PAD(0x01F4, 0x0044, 7, 0x039C, 0, 0),
+
+ MX93_PAD_GPIO_IO14__GPIO2_IO14 = IOMUX_PAD(0x01F8, 0x0048, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO14__LPUART3_TX = IOMUX_PAD(0x01F8, 0x0048, 1, 0x041C, 0, 0),
+ MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 = IOMUX_PAD(0x01F8, 0x0048, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 = IOMUX_PAD(0x01F8, 0x0048, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO14__LPSPI8_SOUT = IOMUX_PAD(0x01F8, 0x0048, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO14__LPUART8_CTS_B = IOMUX_PAD(0x01F8, 0x0048, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO14__LPUART4_TX = IOMUX_PAD(0x01F8, 0x0048, 6, 0x0428, 0, 0),
+ MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 = IOMUX_PAD(0x01F8, 0x0048, 7, 0x03A0, 0, 0),
+
+ MX93_PAD_GPIO_IO15__GPIO2_IO15 = IOMUX_PAD(0x01FC, 0x004C, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO15__LPUART3_RX = IOMUX_PAD(0x01FC, 0x004C, 1, 0x0418, 0, 0),
+ MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 = IOMUX_PAD(0x01FC, 0x004C, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 = IOMUX_PAD(0x01FC, 0x004C, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO15__LPSPI8_SCK = IOMUX_PAD(0x01FC, 0x004C, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO15__LPUART8_RTS_B = IOMUX_PAD(0x01FC, 0x004C, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO15__LPUART4_RX = IOMUX_PAD(0x01FC, 0x004C, 6, 0x0424, 0, 0),
+ MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 = IOMUX_PAD(0x01FC, 0x004C, 7, 0x03A4, 0, 0),
+
+ MX93_PAD_GPIO_IO16__GPIO2_IO16 = IOMUX_PAD(0x0200, 0x0050, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO16__SAI3_TX_BCLK = IOMUX_PAD(0x0200, 0x0050, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 = IOMUX_PAD(0x0200, 0x0050, 2, 0x0440, 1, 0),
+ MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 = IOMUX_PAD(0x0200, 0x0050, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO16__LPUART3_CTS_B = IOMUX_PAD(0x0200, 0x0050, 4, 0x0414, 0, 0),
+ MX93_PAD_GPIO_IO16__LPSPI4_PCS2 = IOMUX_PAD(0x0200, 0x0050, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO16__LPUART4_CTS_B = IOMUX_PAD(0x0200, 0x0050, 6, 0x0420, 0, 0),
+ MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 = IOMUX_PAD(0x0200, 0x0050, 7, 0x03A8, 0, 0),
+
+ MX93_PAD_GPIO_IO17__GPIO2_IO17 = IOMUX_PAD(0x0204, 0x0054, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO17__SAI3_MCLK = IOMUX_PAD(0x0204, 0x0054, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 = IOMUX_PAD(0x0204, 0x0054, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 = IOMUX_PAD(0x0204, 0x0054, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO17__LPUART3_RTS_B = IOMUX_PAD(0x0204, 0x0054, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO17__LPSPI4_PCS1 = IOMUX_PAD(0x0204, 0x0054, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO17__LPUART4_RTS_B = IOMUX_PAD(0x0204, 0x0054, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 = IOMUX_PAD(0x0204, 0x0054, 7, 0x03AC, 0, 0),
+
+ MX93_PAD_GPIO_IO18__GPIO2_IO18 = IOMUX_PAD(0x0208, 0x0058, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO18__SAI3_RX_BCLK = IOMUX_PAD(0x0208, 0x0058, 1, 0x044C, 0, 0),
+ MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 = IOMUX_PAD(0x0208, 0x0058, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 = IOMUX_PAD(0x0208, 0x0058, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO18__LPSPI5_PCS0 = IOMUX_PAD(0x0208, 0x0058, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO18__LPSPI4_PCS0 = IOMUX_PAD(0x0208, 0x0058, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO18__TPM5_CH2 = IOMUX_PAD(0x0208, 0x0058, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 = IOMUX_PAD(0x0208, 0x0058, 7, 0x03B0, 0, 0),
+
+ MX93_PAD_GPIO_IO19__GPIO2_IO19 = IOMUX_PAD(0x020C, 0x005C, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO19__SAI3_RX_SYNC = IOMUX_PAD(0x020C, 0x005C, 1, 0x0450, 1, 0),
+ MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 = IOMUX_PAD(0x020C, 0x005C, 2, 0x0444, 1, 0),
+ MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 = IOMUX_PAD(0x020C, 0x005C, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO19__LPSPI5_SIN = IOMUX_PAD(0x020C, 0x005C, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO19__LPSPI4_SIN = IOMUX_PAD(0x020C, 0x005C, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO19__TPM6_CH2 = IOMUX_PAD(0x020C, 0x005C, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 = IOMUX_PAD(0x020C, 0x005C, 7, 0x0000, 0, 0),
+
+ MX93_PAD_GPIO_IO20__GPIO2_IO20 = IOMUX_PAD(0x0210, 0x0060, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 = IOMUX_PAD(0x0210, 0x0060, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 = IOMUX_PAD(0x0210, 0x0060, 2, 0x0438, 1, 0),
+ MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 = IOMUX_PAD(0x0210, 0x0060, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO20__LPSPI5_SOUT = IOMUX_PAD(0x0210, 0x0060, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO20__LPSPI4_SOUT = IOMUX_PAD(0x0210, 0x0060, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO20__TPM3_CH1 = IOMUX_PAD(0x0210, 0x0060, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 = IOMUX_PAD(0x0210, 0x0060, 7, 0x03B4, 0, 0),
+
+ MX93_PAD_GPIO_IO21__GPIO2_IO21 = IOMUX_PAD(0x0214, 0x0064, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 = IOMUX_PAD(0x0214, 0x0064, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO21__PDM_CLK = IOMUX_PAD(0x0214, 0x0064, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 = IOMUX_PAD(0x0214, 0x0064, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO21__LPSPI5_SCK = IOMUX_PAD(0x0214, 0x0064, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO21__LPSPI4_SCK = IOMUX_PAD(0x0214, 0x0064, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO21__TPM4_CH1 = IOMUX_PAD(0x0214, 0x0064, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO21__SAI3_RX_BCLK = IOMUX_PAD(0x0214, 0x0064, 7, 0x044C, 1, 0),
+
+ MX93_PAD_GPIO_IO22__GPIO2_IO22 = IOMUX_PAD(0x0218, 0x0068, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO22__USDHC3_CLK = IOMUX_PAD(0x0218, 0x0068, 1, 0x0458, 0, 0),
+ MX93_PAD_GPIO_IO22__SPDIF_IN = IOMUX_PAD(0x0218, 0x0068, 2, 0x0454, 0, 0),
+ MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 = IOMUX_PAD(0x0218, 0x0068, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO22__TPM5_CH1 = IOMUX_PAD(0x0218, 0x0068, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO22__TPM6_EXTCLK = IOMUX_PAD(0x0218, 0x0068, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO22__LPI2C5_SDA = IOMUX_PAD(0x0218, 0x0068, 6 | IOMUX_CONFIG_SION, 0x03EC, 1, 0),
+ MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 = IOMUX_PAD(0x0218, 0x0068, 7, 0x03B8, 0, 0),
+
+ MX93_PAD_GPIO_IO23__GPIO2_IO23 = IOMUX_PAD(0x021C, 0x006C, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO23__USDHC3_CMD = IOMUX_PAD(0x021C, 0x006C, 1, 0x045C, 0, 0),
+ MX93_PAD_GPIO_IO23__SPDIF_OUT = IOMUX_PAD(0x021C, 0x006C, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 = IOMUX_PAD(0x021C, 0x006C, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO23__TPM6_CH1 = IOMUX_PAD(0x021C, 0x006C, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO23__LPI2C5_SCL = IOMUX_PAD(0x021C, 0x006C, 6 | IOMUX_CONFIG_SION, 0x03E8, 1, 0),
+ MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 = IOMUX_PAD(0x021C, 0x006C, 7, 0x03BC, 0, 0),
+
+ MX93_PAD_GPIO_IO24__GPIO2_IO24 = IOMUX_PAD(0x0220, 0x0070, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO24__USDHC3_DATA0 = IOMUX_PAD(0x0220, 0x0070, 1, 0x0460, 0, 0),
+ MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 = IOMUX_PAD(0x0220, 0x0070, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO24__TPM3_CH3 = IOMUX_PAD(0x0220, 0x0070, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO24__JTAG_MUX_TDO = IOMUX_PAD(0x0220, 0x0070, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO24__LPSPI6_PCS1 = IOMUX_PAD(0x0220, 0x0070, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 = IOMUX_PAD(0x0220, 0x0070, 7, 0x03C0, 0, 0),
+
+ MX93_PAD_GPIO_IO25__GPIO2_IO25 = IOMUX_PAD(0x0224, 0x0074, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO25__USDHC3_DATA1 = IOMUX_PAD(0x0224, 0x0074, 1, 0x0464, 0, 0),
+ MX93_PAD_GPIO_IO25__CAN2_TX = IOMUX_PAD(0x0224, 0x0074, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 = IOMUX_PAD(0x0224, 0x0074, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO25__TPM4_CH3 = IOMUX_PAD(0x0224, 0x0074, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO25__JTAG_MUX_TCK = IOMUX_PAD(0x0224, 0x0074, 5, 0x03D4, 1, 0),
+ MX93_PAD_GPIO_IO25__LPSPI7_PCS1 = IOMUX_PAD(0x0224, 0x0074, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 = IOMUX_PAD(0x0224, 0x0074, 7, 0x03C4, 0, 0),
+
+ MX93_PAD_GPIO_IO26__GPIO2_IO26 = IOMUX_PAD(0x0228, 0x0078, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO26__USDHC3_DATA2 = IOMUX_PAD(0x0228, 0x0078, 1, 0x0468, 0, 0),
+ MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 = IOMUX_PAD(0x0228, 0x0078, 2, 0x043C, 1, 0),
+ MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 = IOMUX_PAD(0x0228, 0x0078, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO26__TPM5_CH3 = IOMUX_PAD(0x0228, 0x0078, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO26__JTAG_MUX_TDI = IOMUX_PAD(0x0228, 0x0078, 5, 0x03D8, 1, 0),
+ MX93_PAD_GPIO_IO26__LPSPI8_PCS1 = IOMUX_PAD(0x0228, 0x0078, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO26__SAI3_TX_SYNC = IOMUX_PAD(0x0228, 0x0078, 7, 0x0000, 0, 0),
+
+ MX93_PAD_GPIO_IO27__GPIO2_IO27 = IOMUX_PAD(0x022C, 0x007C, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO27__USDHC3_DATA3 = IOMUX_PAD(0x022C, 0x007C, 1, 0x046C, 0, 0),
+ MX93_PAD_GPIO_IO27__CAN2_RX = IOMUX_PAD(0x022C, 0x007C, 2, 0x0364, 1, 0),
+ MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 = IOMUX_PAD(0x022C, 0x007C, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO27__TPM6_CH3 = IOMUX_PAD(0x022C, 0x007C, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO27__JTAG_MUX_TMS = IOMUX_PAD(0x022C, 0x007C, 5, 0x03DC, 1, 0),
+ MX93_PAD_GPIO_IO27__LPSPI5_PCS1 = IOMUX_PAD(0x022C, 0x007C, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 = IOMUX_PAD(0x022C, 0x007C, 7, 0x03C8, 0, 0),
+
+ MX93_PAD_GPIO_IO28__GPIO2_IO28 = IOMUX_PAD(0x0230, 0x0080, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO28__LPI2C3_SDA = IOMUX_PAD(0x0230, 0x0080, 1 | IOMUX_CONFIG_SION, 0x03E4, 1, 0),
+ MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 = IOMUX_PAD(0x0230, 0x0080, 7, 0x0000, 0, 0),
+
+ MX93_PAD_GPIO_IO29__GPIO2_IO29 = IOMUX_PAD(0x0234, 0x0084, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO29__LPI2C3_SCL = IOMUX_PAD(0x0234, 0x0084, 1 | IOMUX_CONFIG_SION, 0x03E0, 1, 0),
+ MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 = IOMUX_PAD(0x0234, 0x0084, 7, 0x0000, 0, 0),
+
+ MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x0238, 0x0088, 0, 0x0000, 0, 0),
+ MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 = IOMUX_PAD(0x0238, 0x0088, 4, 0x0000, 0, 0),
+ MX93_PAD_CCM_CLKO1__GPIO3_IO26 = IOMUX_PAD(0x0238, 0x0088, 5, 0x0000, 0, 0),
+ MX93_PAD_CCM_CLKO2__GPIO3_IO27 = IOMUX_PAD(0x023C, 0x008C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x023C, 0x008C, 0, 0x0000, 0, 0),
+ MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 = IOMUX_PAD(0x023C, 0x008C, 4, 0x03C8, 1, 0),
+
+ MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 = IOMUX_PAD(0x0240, 0x0090, 0, 0x0000, 0, 0),
+ MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 = IOMUX_PAD(0x0240, 0x0090, 4, 0x0000, 0, 0),
+ MX93_PAD_CCM_CLKO3__GPIO4_IO28 = IOMUX_PAD(0x0240, 0x0090, 5, 0x0000, 0, 0),
+
+ MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 = IOMUX_PAD(0x0244, 0x0094, 0, 0x0000, 0, 0),
+ MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 = IOMUX_PAD(0x0244, 0x0094, 4, 0x0000, 0, 0),
+ MX93_PAD_CCM_CLKO4__GPIO4_IO29 = IOMUX_PAD(0x0244, 0x0094, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_MDC__ENET_QOS_MDC = IOMUX_PAD(0x0248, 0x0098, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_MDC__LPUART3_DCB_B = IOMUX_PAD(0x0248, 0x0098, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET1_MDC__I3C2_SCL = IOMUX_PAD(0x0248, 0x0098, 2 | IOMUX_CONFIG_SION, 0x03CC, 0, 0),
+ MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 = IOMUX_PAD(0x0248, 0x0098, 3, 0x0000, 0, 0),
+ MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 = IOMUX_PAD(0x0248, 0x0098, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_MDC__GPIO4_IO00 = IOMUX_PAD(0x0248, 0x0098, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO = IOMUX_PAD(0x024C, 0x009C, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_MDIO__LPUART3_RIN_B = IOMUX_PAD(0x024C, 0x009C, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET1_MDIO__I3C2_SDA = IOMUX_PAD(0x024C, 0x009C, 2 | IOMUX_CONFIG_SION, 0x03D0, 0, 0),
+ MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 = IOMUX_PAD(0x024C, 0x009C, 3, 0x0000, 0, 0),
+ MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 = IOMUX_PAD(0x024C, 0x009C, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_MDIO__GPIO4_IO01 = IOMUX_PAD(0x024C, 0x009C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 = IOMUX_PAD(0x0250, 0x00A0, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD3__CAN2_TX = IOMUX_PAD(0x0250, 0x00A0, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 = IOMUX_PAD(0x0250, 0x00A0, 3, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 = IOMUX_PAD(0x0250, 0x00A0, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD3__GPIO4_IO02 = IOMUX_PAD(0x0250, 0x00A0, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 = IOMUX_PAD(0x0254, 0x00A4, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK = IOMUX_PAD(0x0254, 0x00A4, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD2__CAN2_RX = IOMUX_PAD(0x0254, 0x00A4, 2, 0x0364, 2, 0),
+ MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 = IOMUX_PAD(0x0254, 0x00A4, 3, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 = IOMUX_PAD(0x0254, 0x00A4, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD2__GPIO4_IO03 = IOMUX_PAD(0x0254, 0x00A4, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 = IOMUX_PAD(0x0258, 0x00A8, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD1__LPUART3_RTS_B = IOMUX_PAD(0x0258, 0x00A8, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD1__I3C2_PUR = IOMUX_PAD(0x0258, 0x00A8, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 = IOMUX_PAD(0x0258, 0x00A8, 3, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 = IOMUX_PAD(0x0258, 0x00A8, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD1__GPIO4_IO04 = IOMUX_PAD(0x0258, 0x00A8, 5, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD1__I3C2_PUR_B = IOMUX_PAD(0x0258, 0x00A8, 6, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 = IOMUX_PAD(0x025C, 0x00AC, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD0__LPUART3_TX = IOMUX_PAD(0x025C, 0x00AC, 1, 0x041C, 1, 0),
+ MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 = IOMUX_PAD(0x025C, 0x00AC, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD0__GPIO4_IO05 = IOMUX_PAD(0x025C, 0x00AC, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL = IOMUX_PAD(0x0260, 0x00B0, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B = IOMUX_PAD(0x0260, 0x00B0, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 = IOMUX_PAD(0x0260, 0x00B0, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 = IOMUX_PAD(0x0260, 0x00B0, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK = IOMUX_PAD(0x0264, 0x00B4, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER = IOMUX_PAD(0x0264, 0x00B4, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 = IOMUX_PAD(0x0264, 0x00B4, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TXC__GPIO4_IO07 = IOMUX_PAD(0x0264, 0x00B4, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL = IOMUX_PAD(0x0268, 0x00B8, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B = IOMUX_PAD(0x0268, 0x00B8, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 = IOMUX_PAD(0x0268, 0x00B8, 3, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 = IOMUX_PAD(0x0268, 0x00B8, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 = IOMUX_PAD(0x0268, 0x00B8, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK = IOMUX_PAD(0x026C, 0x00BC, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER = IOMUX_PAD(0x026C, 0x00BC, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 = IOMUX_PAD(0x026C, 0x00BC, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RXC__GPIO4_IO09 = IOMUX_PAD(0x026C, 0x00BC, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 = IOMUX_PAD(0x0270, 0x00C0, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD0__LPUART3_RX = IOMUX_PAD(0x0270, 0x00C0, 1, 0x0418, 1, 0),
+ MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 = IOMUX_PAD(0x0270, 0x00C0, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD0__GPIO4_IO10 = IOMUX_PAD(0x0270, 0x00C0, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 = IOMUX_PAD(0x0274, 0x00C4, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD1__LPUART3_CTS_B = IOMUX_PAD(0x0274, 0x00C4, 1, 0x0414, 1, 0),
+ MX93_PAD_ENET1_RD1__LPTMR2_ALT1 = IOMUX_PAD(0x0274, 0x00C4, 3, 0x0408, 0, 0),
+ MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 = IOMUX_PAD(0x0274, 0x00C4, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD1__GPIO4_IO11 = IOMUX_PAD(0x0274, 0x00C4, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 = IOMUX_PAD(0x0278, 0x00C8, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD2__LPTMR2_ALT2 = IOMUX_PAD(0x0278, 0x00C8, 3, 0x040C, 0, 0),
+ MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 = IOMUX_PAD(0x0278, 0x00C8, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD2__GPIO4_IO12 = IOMUX_PAD(0x0278, 0x00C8, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 = IOMUX_PAD(0x027C, 0x00CC, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER = IOMUX_PAD(0x027C, 0x00CC, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD3__LPTMR2_ALT3 = IOMUX_PAD(0x027C, 0x00CC, 3, 0x0410, 0, 0),
+ MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 = IOMUX_PAD(0x027C, 0x00CC, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD3__GPIO4_IO13 = IOMUX_PAD(0x027C, 0x00CC, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_MDC__ENET1_MDC = IOMUX_PAD(0x0280, 0x00D0, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_MDC__LPUART4_DCB_B = IOMUX_PAD(0x0280, 0x00D0, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_MDC__SAI2_RX_SYNC = IOMUX_PAD(0x0280, 0x00D0, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 = IOMUX_PAD(0x0280, 0x00D0, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_MDC__GPIO4_IO14 = IOMUX_PAD(0x0280, 0x00D0, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_MDIO__ENET1_MDIO = IOMUX_PAD(0x0284, 0x00D4, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_MDIO__LPUART4_RIN_B = IOMUX_PAD(0x0284, 0x00D4, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK = IOMUX_PAD(0x0284, 0x00D4, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 = IOMUX_PAD(0x0284, 0x00D4, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_MDIO__GPIO4_IO15 = IOMUX_PAD(0x0284, 0x00D4, 5, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD3__SAI2_RX_DATA00 = IOMUX_PAD(0x0288, 0x00D8, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 = IOMUX_PAD(0x0288, 0x00D8, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD3__GPIO4_IO16 = IOMUX_PAD(0x0288, 0x00D8, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x0288, 0x00D8, 0, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x028C, 0x00DC, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD2__ENET1_TX_CLK = IOMUX_PAD(0x028C, 0x00DC, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD2__SAI2_RX_DATA01 = IOMUX_PAD(0x028C, 0x00DC, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 = IOMUX_PAD(0x028C, 0x00DC, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD2__GPIO4_IO17 = IOMUX_PAD(0x028C, 0x00DC, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x0290, 0x00E0, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD1__LPUART4_RTS_B = IOMUX_PAD(0x0290, 0x00E0, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD1__SAI2_RX_DATA02 = IOMUX_PAD(0x0290, 0x00E0, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 = IOMUX_PAD(0x0290, 0x00E0, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD1__GPIO4_IO18 = IOMUX_PAD(0x0290, 0x00E0, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x0294, 0x00E4, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD0__LPUART4_TX = IOMUX_PAD(0x0294, 0x00E4, 1, 0x0428, 1, 0),
+ MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 = IOMUX_PAD(0x0294, 0x00E4, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 = IOMUX_PAD(0x0294, 0x00E4, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD0__GPIO4_IO19 = IOMUX_PAD(0x0294, 0x00E4, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x0298, 0x00E8, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B = IOMUX_PAD(0x0298, 0x00E8, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC = IOMUX_PAD(0x0298, 0x00E8, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 = IOMUX_PAD(0x0298, 0x00E8, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 = IOMUX_PAD(0x0298, 0x00E8, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x029C, 0x00EC, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TXC__ENET1_TX_ER = IOMUX_PAD(0x029C, 0x00EC, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x029C, 0x00EC, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 = IOMUX_PAD(0x029C, 0x00EC, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TXC__GPIO4_IO21 = IOMUX_PAD(0x029C, 0x00EC, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x02A0, 0x00F0, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B = IOMUX_PAD(0x02A0, 0x00F0, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 = IOMUX_PAD(0x02A0, 0x00F0, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 = IOMUX_PAD(0x02A0, 0x00F0, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 = IOMUX_PAD(0x02A0, 0x00F0, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC = IOMUX_PAD(0x02A4, 0x00F4, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RXC__ENET1_RX_ER = IOMUX_PAD(0x02A4, 0x00F4, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RXC__SAI2_TX_DATA01 = IOMUX_PAD(0x02A4, 0x00F4, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 = IOMUX_PAD(0x02A4, 0x00F4, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RXC__GPIO4_IO23 = IOMUX_PAD(0x02A4, 0x00F4, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 = IOMUX_PAD(0x02A8, 0x00F8, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD0__LPUART4_RX = IOMUX_PAD(0x02A8, 0x00F8, 1, 0x0424, 1, 0),
+ MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 = IOMUX_PAD(0x02A8, 0x00F8, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 = IOMUX_PAD(0x02A8, 0x00F8, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD0__GPIO4_IO24 = IOMUX_PAD(0x02A8, 0x00F8, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 = IOMUX_PAD(0x02AC, 0x00FC, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD1__SPDIF_IN = IOMUX_PAD(0x02AC, 0x00FC, 1, 0x0454, 1, 0),
+ MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 = IOMUX_PAD(0x02AC, 0x00FC, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 = IOMUX_PAD(0x02AC, 0x00FC, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD1__GPIO4_IO25 = IOMUX_PAD(0x02AC, 0x00FC, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 = IOMUX_PAD(0x02B0, 0x0100, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD2__LPUART4_CTS_B = IOMUX_PAD(0x02B0, 0x0100, 1, 0x0420, 1, 0),
+ MX93_PAD_ENET2_RD2__SAI2_MCLK = IOMUX_PAD(0x02B0, 0x0100, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD2__MQS2_RIGHT = IOMUX_PAD(0x02B0, 0x0100, 3, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 = IOMUX_PAD(0x02B0, 0x0100, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD2__GPIO4_IO26 = IOMUX_PAD(0x02B0, 0x0100, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 = IOMUX_PAD(0x02B4, 0x0104, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD3__SPDIF_OUT = IOMUX_PAD(0x02B4, 0x0104, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD3__SPDIF_IN = IOMUX_PAD(0x02B4, 0x0104, 2, 0x0454, 2, 0),
+ MX93_PAD_ENET2_RD3__MQS2_LEFT = IOMUX_PAD(0x02B4, 0x0104, 3, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 = IOMUX_PAD(0x02B4, 0x0104, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD3__GPIO4_IO27 = IOMUX_PAD(0x02B4, 0x0104, 5, 0x0000, 0, 0),
+ MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08 = IOMUX_PAD(0x02B8, 0x0108, 4, 0x038C, 1, 0),
+ MX93_PAD_SD1_CLK__GPIO3_IO08 = IOMUX_PAD(0x02B8, 0x0108, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x02B8, 0x0108, 0, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x02BC, 0x010C, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09 = IOMUX_PAD(0x02BC, 0x010C, 4, 0x0390, 1, 0),
+ MX93_PAD_SD1_CMD__GPIO3_IO09 = IOMUX_PAD(0x02BC, 0x010C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x02C0, 0x0110, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 = IOMUX_PAD(0x02C0, 0x0110, 4, 0x0394, 1, 0),
+ MX93_PAD_SD1_DATA0__GPIO3_IO10 = IOMUX_PAD(0x02C0, 0x0110, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x02C4, 0x0114, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 = IOMUX_PAD(0x02C4, 0x0114, 4, 0x0398, 1, 0),
+ MX93_PAD_SD1_DATA1__GPIO3_IO11 = IOMUX_PAD(0x02C4, 0x0114, 5, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT = IOMUX_PAD(0x02C4, 0x0114, 6, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x02C8, 0x0118, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 = IOMUX_PAD(0x02C8, 0x0118, 4, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA2__GPIO3_IO12 = IOMUX_PAD(0x02C8, 0x0118, 5, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x02C8, 0x0118, 6, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x02CC, 0x011C, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B = IOMUX_PAD(0x02CC, 0x011C, 1, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 = IOMUX_PAD(0x02CC, 0x011C, 4, 0x039C, 1, 0),
+ MX93_PAD_SD1_DATA3__GPIO3_IO13 = IOMUX_PAD(0x02CC, 0x011C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x02D0, 0x0120, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 = IOMUX_PAD(0x02D0, 0x0120, 1, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 = IOMUX_PAD(0x02D0, 0x0120, 4, 0x03A0, 1, 0),
+ MX93_PAD_SD1_DATA4__GPIO3_IO14 = IOMUX_PAD(0x02D0, 0x0120, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x02D4, 0x0124, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 = IOMUX_PAD(0x02D4, 0x0124, 1, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA5__USDHC1_RESET_B = IOMUX_PAD(0x02D4, 0x0124, 2, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 = IOMUX_PAD(0x02D4, 0x0124, 4, 0x03A4, 1, 0),
+ MX93_PAD_SD1_DATA5__GPIO3_IO15 = IOMUX_PAD(0x02D4, 0x0124, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x02D8, 0x0128, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 = IOMUX_PAD(0x02D8, 0x0128, 1, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA6__USDHC1_CD_B = IOMUX_PAD(0x02D8, 0x0128, 2, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 = IOMUX_PAD(0x02D8, 0x0128, 4, 0x03A8, 1, 0),
+ MX93_PAD_SD1_DATA6__GPIO3_IO16 = IOMUX_PAD(0x02D8, 0x0128, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x02DC, 0x012C, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 = IOMUX_PAD(0x02DC, 0x012C, 1, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA7__USDHC1_WP = IOMUX_PAD(0x02DC, 0x012C, 2, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 = IOMUX_PAD(0x02DC, 0x012C, 4, 0x03AC, 1, 0),
+ MX93_PAD_SD1_DATA7__GPIO3_IO17 = IOMUX_PAD(0x02DC, 0x012C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x02E0, 0x0130, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS = IOMUX_PAD(0x02E0, 0x0130, 1, 0x0000, 0, 0),
+ MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 = IOMUX_PAD(0x02E0, 0x0130, 4, 0x03B0, 1, 0),
+ MX93_PAD_SD1_STROBE__GPIO3_IO18 = IOMUX_PAD(0x02E0, 0x0130, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT = IOMUX_PAD(0x02E4, 0x0134, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_VSELECT__USDHC2_WP = IOMUX_PAD(0x02E4, 0x0134, 1, 0x0000, 0, 0),
+ MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 = IOMUX_PAD(0x02E4, 0x0134, 2, 0x0410, 1, 0),
+ MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 = IOMUX_PAD(0x02E4, 0x0134, 4, 0x0000, 0, 0),
+ MX93_PAD_SD2_VSELECT__GPIO3_IO19 = IOMUX_PAD(0x02E4, 0x0134, 5, 0x0000, 0, 0),
+ MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x02E4, 0x0134, 6, 0x0368, 0, 0),
+
+ MX93_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x02E8, 0x0138, 0, 0x0458, 1, 0),
+ MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK = IOMUX_PAD(0x02E8, 0x0138, 1, 0x0000, 0, 0),
+ MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 = IOMUX_PAD(0x02E8, 0x0138, 4, 0x03B4, 1, 0),
+ MX93_PAD_SD3_CLK__GPIO3_IO20 = IOMUX_PAD(0x02E8, 0x0138, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x02EC, 0x013C, 0, 0x045C, 1, 0),
+ MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B = IOMUX_PAD(0x02EC, 0x013C, 1, 0x0000, 0, 0),
+ MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 = IOMUX_PAD(0x02EC, 0x013C, 4, 0x0000, 0, 0),
+ MX93_PAD_SD3_CMD__GPIO3_IO21 = IOMUX_PAD(0x02EC, 0x013C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD3_DATA0__USDHC3_DATA0 = IOMUX_PAD(0x02F0, 0x0140, 0, 0x0460, 1, 0),
+ MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 = IOMUX_PAD(0x02F0, 0x0140, 1, 0x0000, 0, 0),
+ MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 = IOMUX_PAD(0x02F0, 0x0140, 4, 0x03B8, 1, 0),
+ MX93_PAD_SD3_DATA0__GPIO3_IO22 = IOMUX_PAD(0x02F0, 0x0140, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD3_DATA1__USDHC3_DATA1 = IOMUX_PAD(0x02F4, 0x0144, 0, 0x0464, 1, 0),
+ MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 = IOMUX_PAD(0x02F4, 0x0144, 1, 0x0000, 0, 0),
+ MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 = IOMUX_PAD(0x02F4, 0x0144, 4, 0x03BC, 1, 0),
+ MX93_PAD_SD3_DATA1__GPIO3_IO23 = IOMUX_PAD(0x02F4, 0x0144, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD3_DATA2__USDHC3_DATA2 = IOMUX_PAD(0x02F8, 0x0148, 0, 0x0468, 1, 0),
+ MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 = IOMUX_PAD(0x02F8, 0x0148, 1, 0x0000, 0, 0),
+ MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 = IOMUX_PAD(0x02F8, 0x0148, 4, 0x03C0, 1, 0),
+ MX93_PAD_SD3_DATA2__GPIO3_IO24 = IOMUX_PAD(0x02F8, 0x0148, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD3_DATA3__USDHC3_DATA3 = IOMUX_PAD(0x02FC, 0x014C, 0, 0x046C, 1, 0),
+ MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 = IOMUX_PAD(0x02FC, 0x014C, 1, 0x0000, 0, 0),
+ MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 = IOMUX_PAD(0x02FC, 0x014C, 4, 0x03C4, 1, 0),
+ MX93_PAD_SD3_DATA3__GPIO3_IO25 = IOMUX_PAD(0x02FC, 0x014C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0300, 0x0150, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN = IOMUX_PAD(0x0300, 0x0150, 1, 0x0000, 0, 0),
+ MX93_PAD_SD2_CD_B__I3C2_SCL = IOMUX_PAD(0x0300, 0x0150, 2 | IOMUX_CONFIG_SION, 0x03CC, 1, 0),
+ MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 = IOMUX_PAD(0x0300, 0x0150, 4, 0x036C, 1, 0),
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 = IOMUX_PAD(0x0300, 0x0150, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x0304, 0x0154, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT = IOMUX_PAD(0x0304, 0x0154, 1, 0x0000, 0, 0),
+ MX93_PAD_SD2_CLK__I3C2_SDA = IOMUX_PAD(0x0304, 0x0154, 2 | IOMUX_CONFIG_SION, 0x03D0, 1, 0),
+ MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 = IOMUX_PAD(0x0304, 0x0154, 4, 0x0370, 1, 0),
+ MX93_PAD_SD2_CLK__GPIO3_IO01 = IOMUX_PAD(0x0304, 0x0154, 5, 0x0000, 0, 0),
+ MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 = IOMUX_PAD(0x0304, 0x0154, 6, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0308, 0x0158, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x0308, 0x0158, 1, 0x0000, 0, 0),
+ MX93_PAD_SD2_CMD__I3C2_PUR = IOMUX_PAD(0x0308, 0x0158, 2, 0x0000, 0, 0),
+ MX93_PAD_SD2_CMD__I3C2_PUR_B = IOMUX_PAD(0x0308, 0x0158, 3, 0x0000, 0, 0),
+ MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02 = IOMUX_PAD(0x0308, 0x0158, 4, 0x0374, 1, 0),
+ MX93_PAD_SD2_CMD__GPIO3_IO02 = IOMUX_PAD(0x0308, 0x0158, 5, 0x0000, 0, 0),
+ MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 = IOMUX_PAD(0x0308, 0x0158, 6, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x030C, 0x015C, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x030C, 0x015C, 1, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA0__CAN2_TX = IOMUX_PAD(0x030C, 0x015C, 2, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 = IOMUX_PAD(0x030C, 0x015C, 4, 0x0378, 1, 0),
+ MX93_PAD_SD2_DATA0__GPIO3_IO03 = IOMUX_PAD(0x030C, 0x015C, 5, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 = IOMUX_PAD(0x030C, 0x015C, 6, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0310, 0x0160, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0310, 0x0160, 1, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA1__CAN2_RX = IOMUX_PAD(0x0310, 0x0160, 2, 0x0364, 3, 0),
+ MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 = IOMUX_PAD(0x0310, 0x0160, 4, 0x037C, 1, 0),
+ MX93_PAD_SD2_DATA1__GPIO3_IO04 = IOMUX_PAD(0x0310, 0x0160, 5, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x0310, 0x0160, 6, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x0314, 0x0164, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0314, 0x0164, 1, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA2__MQS2_RIGHT = IOMUX_PAD(0x0314, 0x0164, 2, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 = IOMUX_PAD(0x0314, 0x0164, 4, 0x0380, 1, 0),
+ MX93_PAD_SD2_DATA2__GPIO3_IO05 = IOMUX_PAD(0x0314, 0x0164, 5, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x0314, 0x0164, 6, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0318, 0x0168, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA3__LPTMR2_ALT1 = IOMUX_PAD(0x0318, 0x0168, 1, 0x0408, 1, 0),
+ MX93_PAD_SD2_DATA3__MQS2_LEFT = IOMUX_PAD(0x0318, 0x0168, 2, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 = IOMUX_PAD(0x0318, 0x0168, 4, 0x0384, 1, 0),
+ MX93_PAD_SD2_DATA3__GPIO3_IO06 = IOMUX_PAD(0x0318, 0x0168, 5, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET = IOMUX_PAD(0x0318, 0x0168, 6, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x031C, 0x016C, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 = IOMUX_PAD(0x031C, 0x016C, 1, 0x040C, 1, 0),
+ MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 = IOMUX_PAD(0x031C, 0x016C, 4, 0x0388, 1, 0),
+ MX93_PAD_SD2_RESET_B__GPIO3_IO07 = IOMUX_PAD(0x031C, 0x016C, 5, 0x0000, 0, 0),
+ MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET = IOMUX_PAD(0x031C, 0x016C, 6, 0x0000, 0, 0),
+
+ MX93_PAD_I2C1_SCL__LPI2C1_SCL = IOMUX_PAD(0x0320, 0x0170, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX93_PAD_I2C1_SCL__I3C1_SCL = IOMUX_PAD(0x0320, 0x0170, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX93_PAD_I2C1_SCL__LPUART1_DCB_B = IOMUX_PAD(0x0320, 0x0170, 2, 0x0000, 0, 0),
+ MX93_PAD_I2C1_SCL__TPM2_CH0 = IOMUX_PAD(0x0320, 0x0170, 3, 0x0000, 0, 0),
+ MX93_PAD_I2C1_SCL__GPIO1_IO00 = IOMUX_PAD(0x0320, 0x0170, 5, 0x0000, 0, 0),
+
+ MX93_PAD_I2C1_SDA__LPI2C1_SDA = IOMUX_PAD(0x0324, 0x0174, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX93_PAD_I2C1_SDA__I3C1_SDA = IOMUX_PAD(0x0324, 0x0174, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX93_PAD_I2C1_SDA__LPUART1_RIN_B = IOMUX_PAD(0x0324, 0x0174, 2, 0x0000, 0, 0),
+ MX93_PAD_I2C1_SDA__TPM2_CH1 = IOMUX_PAD(0x0324, 0x0174, 3, 0x0000, 0, 0),
+ MX93_PAD_I2C1_SDA__GPIO1_IO01 = IOMUX_PAD(0x0324, 0x0174, 5, 0x0000, 0, 0),
+
+ MX93_PAD_I2C2_SCL__LPI2C2_SCL = IOMUX_PAD(0x0328, 0x0178, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SCL__I3C1_PUR = IOMUX_PAD(0x0328, 0x0178, 1, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SCL__LPUART2_DCB_B = IOMUX_PAD(0x0328, 0x0178, 2, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SCL__TPM2_CH2 = IOMUX_PAD(0x0328, 0x0178, 3, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SCL__SAI1_RX_SYNC = IOMUX_PAD(0x0328, 0x0178, 4, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SCL__GPIO1_IO02 = IOMUX_PAD(0x0328, 0x0178, 5, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SCL__I3C1_PUR_B = IOMUX_PAD(0x0328, 0x0178, 6, 0x0000, 0, 0),
+
+ MX93_PAD_I2C2_SDA__LPI2C2_SDA = IOMUX_PAD(0x032C, 0x017C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SDA__LPUART2_RIN_B = IOMUX_PAD(0x032C, 0x017C, 2, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SDA__TPM2_CH3 = IOMUX_PAD(0x032C, 0x017C, 3, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SDA__SAI1_RX_BCLK = IOMUX_PAD(0x032C, 0x017C, 4, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SDA__GPIO1_IO03 = IOMUX_PAD(0x032C, 0x017C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_UART1_RXD__LPUART1_RX = IOMUX_PAD(0x0330, 0x0180, 0, 0x0000, 0, 0),
+ MX93_PAD_UART1_RXD__S400_UART_RX = IOMUX_PAD(0x0330, 0x0180, 1, 0x0000, 0, 0),
+ MX93_PAD_UART1_RXD__LPSPI2_SIN = IOMUX_PAD(0x0330, 0x0180, 2, 0x0000, 0, 0),
+ MX93_PAD_UART1_RXD__TPM1_CH0 = IOMUX_PAD(0x0330, 0x0180, 3, 0x0000, 0, 0),
+ MX93_PAD_UART1_RXD__GPIO1_IO04 = IOMUX_PAD(0x0330, 0x0180, 5, 0x0000, 0, 0),
+
+ MX93_PAD_UART1_TXD__LPUART1_TX = IOMUX_PAD(0x0334, 0x0184, 0, 0x0000, 0, 0),
+ MX93_PAD_UART1_TXD__S400_UART_TX = IOMUX_PAD(0x0334, 0x0184, 1, 0x0000, 0, 0),
+ MX93_PAD_UART1_TXD__LPSPI2_PCS0 = IOMUX_PAD(0x0334, 0x0184, 2, 0x0000, 0, 0),
+ MX93_PAD_UART1_TXD__TPM1_CH1 = IOMUX_PAD(0x0334, 0x0184, 3, 0x0000, 0, 0),
+ MX93_PAD_UART1_TXD__GPIO1_IO05 = IOMUX_PAD(0x0334, 0x0184, 5, 0x0000, 0, 0),
+
+ MX93_PAD_UART2_RXD__LPUART2_RX = IOMUX_PAD(0x0338, 0x0188, 0, 0x0000, 0, 0),
+ MX93_PAD_UART2_RXD__LPUART1_CTS_B = IOMUX_PAD(0x0338, 0x0188, 1, 0x0000, 0, 0),
+ MX93_PAD_UART2_RXD__LPSPI2_SOUT = IOMUX_PAD(0x0338, 0x0188, 2, 0x0000, 0, 0),
+ MX93_PAD_UART2_RXD__TPM1_CH2 = IOMUX_PAD(0x0338, 0x0188, 3, 0x0000, 0, 0),
+ MX93_PAD_UART2_RXD__SAI1_MCLK = IOMUX_PAD(0x0338, 0x0188, 4, 0x0448, 0, 0),
+ MX93_PAD_UART2_RXD__GPIO1_IO06 = IOMUX_PAD(0x0338, 0x0188, 5, 0x0000, 0, 0),
+
+ MX93_PAD_UART2_TXD__LPUART2_TX = IOMUX_PAD(0x033C, 0x018C, 0, 0x0000, 0, 0),
+ MX93_PAD_UART2_TXD__LPUART1_RTS_B = IOMUX_PAD(0x033C, 0x018C, 1, 0x0000, 0, 0),
+ MX93_PAD_UART2_TXD__LPSPI2_SCK = IOMUX_PAD(0x033C, 0x018C, 2, 0x0000, 0, 0),
+ MX93_PAD_UART2_TXD__TPM1_CH3 = IOMUX_PAD(0x033C, 0x018C, 3, 0x0000, 0, 0),
+ MX93_PAD_UART2_TXD__GPIO1_IO07 = IOMUX_PAD(0x033C, 0x018C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_PDM_CLK__PDM_CLK = IOMUX_PAD(0x0340, 0x0190, 0, 0x0000, 0, 0),
+ MX93_PAD_PDM_CLK__MQS1_LEFT = IOMUX_PAD(0x0340, 0x0190, 1, 0x0000, 0, 0),
+ MX93_PAD_PDM_CLK__LPTMR1_ALT1 = IOMUX_PAD(0x0340, 0x0190, 4, 0x0000, 0, 0),
+ MX93_PAD_PDM_CLK__GPIO1_IO08 = IOMUX_PAD(0x0340, 0x0190, 5, 0x0000, 0, 0),
+ MX93_PAD_PDM_CLK__CAN1_TX = IOMUX_PAD(0x0340, 0x0190, 6, 0x0000, 0, 0),
+
+ MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 = IOMUX_PAD(0x0344, 0x0194, 0, 0x0438, 2, 0),
+ MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT = IOMUX_PAD(0x0344, 0x0194, 1, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 = IOMUX_PAD(0x0344, 0x0194, 2, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK = IOMUX_PAD(0x0344, 0x0194, 3, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 = IOMUX_PAD(0x0344, 0x0194, 4, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 = IOMUX_PAD(0x0344, 0x0194, 5, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM0__CAN1_RX = IOMUX_PAD(0x0344, 0x0194, 6, 0x0360, 0, 0),
+
+ MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 = IOMUX_PAD(0x0348, 0x0198, 0, 0x043C, 2, 0),
+ MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI = IOMUX_PAD(0x0348, 0x0198, 1, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 = IOMUX_PAD(0x0348, 0x0198, 2, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK = IOMUX_PAD(0x0348, 0x0198, 3, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 = IOMUX_PAD(0x0348, 0x0198, 4, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 = IOMUX_PAD(0x0348, 0x0198, 5, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x0348, 0x0198, 6, 0x0368, 1, 0),
+
+ MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x034C, 0x019C, 0, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01 = IOMUX_PAD(0x034C, 0x019C, 1, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 = IOMUX_PAD(0x034C, 0x019C, 2, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXFS__LPUART2_DTR_B = IOMUX_PAD(0x034C, 0x019C, 3, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXFS__MQS1_LEFT = IOMUX_PAD(0x034C, 0x019C, 4, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXFS__GPIO1_IO11 = IOMUX_PAD(0x034C, 0x019C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x0350, 0x01A0, 0, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXC__LPUART2_CTS_B = IOMUX_PAD(0x0350, 0x01A0, 1, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXC__LPSPI1_SIN = IOMUX_PAD(0x0350, 0x01A0, 2, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXC__LPUART1_DSR_B = IOMUX_PAD(0x0350, 0x01A0, 3, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXC__CAN1_RX = IOMUX_PAD(0x0350, 0x01A0, 4, 0x0360, 1, 0),
+ MX93_PAD_SAI1_TXC__GPIO1_IO12 = IOMUX_PAD(0x0350, 0x01A0, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 = IOMUX_PAD(0x0354, 0x01A4, 0, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXD0__LPUART2_RTS_B = IOMUX_PAD(0x0354, 0x01A4, 1, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXD0__LPSPI1_SCK = IOMUX_PAD(0x0354, 0x01A4, 2, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXD0__LPUART1_DTR_B = IOMUX_PAD(0x0354, 0x01A4, 3, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXD0__CAN1_TX = IOMUX_PAD(0x0354, 0x01A4, 4, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXD0__GPIO1_IO13 = IOMUX_PAD(0x0354, 0x01A4, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 = IOMUX_PAD(0x0358, 0x01A8, 0, 0x0000, 0, 0),
+ MX93_PAD_SAI1_RXD0__SAI1_MCLK = IOMUX_PAD(0x0358, 0x01A8, 1, 0x0448, 1, 0),
+ MX93_PAD_SAI1_RXD0__LPSPI1_SOUT = IOMUX_PAD(0x0358, 0x01A8, 2, 0x0000, 0, 0),
+ MX93_PAD_SAI1_RXD0__LPUART2_DSR_B = IOMUX_PAD(0x0358, 0x01A8, 3, 0x0000, 0, 0),
+ MX93_PAD_SAI1_RXD0__MQS1_RIGHT = IOMUX_PAD(0x0358, 0x01A8, 4, 0x0000, 0, 0),
+ MX93_PAD_SAI1_RXD0__GPIO1_IO14 = IOMUX_PAD(0x0358, 0x01A8, 5, 0x0000, 0, 0),
+
+ MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY = IOMUX_PAD(0x035C, 0x01AC, 0, 0x0000, 0, 0),
+ MX93_PAD_WDOG_ANY__GPIO1_IO15 = IOMUX_PAD(0x035C, 0x01AC, 5, 0x0000, 0, 0),
+};
+#endif /* __ASM_ARCH_IMX93_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h
new file mode 100644
index 0000000000..292635982f
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 NXP
+ */
+
+#ifndef __ARCH_IMX9_SYS_PROTO_H
+#define __ARCH_NMX9_SYS_PROTO_H
+
+#include <asm/mach-imx/sys_proto.h>
+
+ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf);
+ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
+extern unsigned long rom_pointer[];
+enum boot_device get_boot_device(void);
+bool is_usb_boot(void);
+int mix_power_init(enum mix_power_domain pd);
+void soc_power_init(void);
+bool m33_is_rom_kicked(void);
+int m33_prepare(void);
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/trdc.h b/arch/arm/include/asm/arch-imx9/trdc.h
new file mode 100644
index 0000000000..7c984d9ce9
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/trdc.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_TRDC_H
+#define __ASM_ARCH_IMX9_TRDC_H
+
+int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x,
+ u32 glbac_id, u32 glbac_val);
+int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x,
+ u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access, u32 glbac_id);
+int trdc_mrc_set_control(ulong trdc_reg, u32 mrc_x,
+ u32 glbac_id, u32 glbac_val);
+int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x,
+ u32 dom_x, u32 addr_start, u32 addr_end, bool sec_access, u32 glbac_id);
+
+void trdc_early_init(void);
+void trdc_init(void);
+
+#endif
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 085e12b5d4..8d25c32c3a 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -90,10 +90,16 @@ struct arch_global_data {
struct udevice *scu_dev;
#endif
-#ifdef CONFIG_ARCH_IMX8ULP
+#ifdef CONFIG_IMX_SENTINEL
struct udevice *s400_dev;
+ u32 soc_rev;
+ u32 lifecycle;
+ u32 uid[4];
#endif
+#ifdef CONFIG_ARCH_IMX8ULP
+ bool m33_handshake_done;
+#endif
};
#include <asm-generic/global_data.h>
diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h
index dcf9bd8966..cd2c6e73e0 100644
--- a/arch/arm/include/asm/mach-imx/iomux-v3.h
+++ b/arch/arm/include/asm/mach-imx/iomux-v3.h
@@ -86,7 +86,16 @@ typedef u64 iomux_v3_cfg_t;
#define IOMUX_CONFIG_LPSR 0x20
#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
MUX_MODE_SHIFT)
-#ifdef CONFIG_IMX8M
+#ifdef CONFIG_IMX93
+#define PAD_CTL_FSEL2 (0x2 << 7)
+#define PAD_CTL_FSEL3 (0x3 << 7)
+#define PAD_CTL_PUE (0x1 << 9)
+#define PAD_CTL_PDE (0x1 << 10)
+#define PAD_CTL_ODE (0x1 << 11)
+#define PAD_CTL_HYS (0x1 << 12)
+#define PAD_CTL_DSE(x) (((x) << 1) & 0x7f)
+
+#elif defined(CONFIG_IMX8M)
#define PAD_CTL_FSEL0 (0x0 << 3)
#define PAD_CTL_FSEL1 (0x1 << 3)
#define PAD_CTL_FSEL2 (0x2 << 3)
diff --git a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h b/arch/arm/include/asm/mach-imx/mu_hal.h
index 10d966d5d4..5db559c1ac 100644
--- a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h
+++ b/arch/arm/include/asm/mach-imx/mu_hal.h
@@ -3,8 +3,8 @@
* Copyright 2021 NXP
*/
-#ifndef __IMX8ULP_MU_HAL_H__
-#define __IMX8ULP_MU_HAL_H__
+#ifndef __SNT_MU_HAL_H__
+#define __SNT_MU_HAL_H__
void mu_hal_init(ulong base);
int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg);
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h
new file mode 100644
index 0000000000..9e3c8136df
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -0,0 +1,148 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef __S400_API_H__
+#define __S400_API_H__
+
+#define AHAB_VERSION 0x6
+#define AHAB_CMD_TAG 0x17
+#define AHAB_RESP_TAG 0xe1
+
+/* ELE commands */
+#define ELE_PING_REQ (0x01)
+#define ELE_FW_AUTH_REQ (0x02)
+#define ELE_RESTART_RST_TIMER_REQ (0x04)
+#define ELE_DUMP_DEBUG_BUFFER_REQ (0x21)
+#define ELE_OEM_CNTN_AUTH_REQ (0x87)
+#define ELE_VERIFY_IMAGE_REQ (0x88)
+#define ELE_RELEASE_CONTAINER_REQ (0x89)
+#define ELE_WRITE_SECURE_FUSE_REQ (0x91)
+#define ELE_FWD_LIFECYCLE_UP_REQ (0x95)
+#define ELE_READ_FUSE_REQ (0x97)
+#define ELE_GET_FW_VERSION_REQ (0x9D)
+#define ELE_RET_LIFECYCLE_UP_REQ (0xA0)
+#define ELE_GET_EVENTS_REQ (0xA2)
+#define ELE_START_RNG (0xA3)
+#define ELE_ENABLE_PATCH_REQ (0xC3)
+#define ELE_RELEASE_RDC_REQ (0xC4)
+#define ELE_GET_FW_STATUS_REQ (0xC5)
+#define ELE_ENABLE_OTFAD_REQ (0xC6)
+#define ELE_RESET_REQ (0xC7)
+#define ELE_UPDATE_OTP_CLKDIV_REQ (0xD0)
+#define ELE_POWER_DOWN_REQ (0xD1)
+#define ELE_ENABLE_APC_REQ (0xD2)
+#define ELE_ENABLE_RTC_REQ (0xD3)
+#define ELE_DEEP_POWER_DOWN_REQ (0xD4)
+#define ELE_STOP_RST_TIMER_REQ (0xD5)
+#define ELE_WRITE_FUSE_REQ (0xD6)
+#define ELE_RELEASE_CAAM_REQ (0xD7)
+#define ELE_RESET_A35_CTX_REQ (0xD8)
+#define ELE_MOVE_TO_UNSECURED_REQ (0xD9)
+#define ELE_GET_INFO_REQ (0xDA)
+#define ELE_ATTEST_REQ (0xDB)
+#define ELE_RELEASE_PATCH_REQ (0xDC)
+#define ELE_OTP_SEQ_SWITH_REQ (0xDD)
+
+/* ELE failure indications */
+#define ELE_ROM_PING_FAILURE_IND (0x0A)
+#define ELE_FW_PING_FAILURE_IND (0x1A)
+#define ELE_BAD_SIGNATURE_FAILURE_IND (0xF0)
+#define ELE_BAD_HASH_FAILURE_IND (0xF1)
+#define ELE_INVALID_LIFECYCLE_IND (0xF2)
+#define ELE_PERMISSION_DENIED_FAILURE_IND (0xF3)
+#define ELE_INVALID_MESSAGE_FAILURE_IND (0xF4)
+#define ELE_BAD_VALUE_FAILURE_IND (0xF5)
+#define ELE_BAD_FUSE_ID_FAILURE_IND (0xF6)
+#define ELE_BAD_CONTAINER_FAILURE_IND (0xF7)
+#define ELE_BAD_VERSION_FAILURE_IND (0xF8)
+#define ELE_INVALID_KEY_FAILURE_IND (0xF9)
+#define ELE_BAD_KEY_HASH_FAILURE_IND (0xFA)
+#define ELE_NO_VALID_CONTAINER_FAILURE_IND (0xFB)
+#define ELE_BAD_CERTIFICATE_FAILURE_IND (0xFC)
+#define ELE_BAD_UID_FAILURE_IND (0xFD)
+#define ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND (0xFE)
+#define ELE_MUST_SIGNED_FAILURE_IND (0xE0)
+#define ELE_NO_AUTHENTICATION_FAILURE_IND (0xEE)
+#define ELE_BAD_SRK_SET_FAILURE_IND (0xEF)
+#define ELE_UNALIGNED_PAYLOAD_FAILURE_IND (0xA6)
+#define ELE_WRONG_SIZE_FAILURE_IND (0xA7)
+#define ELE_ENCRYPTION_FAILURE_IND (0xA8)
+#define ELE_DECRYPTION_FAILURE_IND (0xA9)
+#define ELE_OTP_PROGFAIL_FAILURE_IND (0xAA)
+#define ELE_OTP_LOCKED_FAILURE_IND (0xAB)
+#define ELE_OTP_INVALID_IDX_FAILURE_IND (0xAD)
+#define ELE_TIME_OUT_FAILURE_IND (0xB0)
+#define ELE_BAD_PAYLOAD_FAILURE_IND (0xB1)
+#define ELE_WRONG_ADDRESS_FAILURE_IND (0xB4)
+#define ELE_DMA_FAILURE_IND (0xB5)
+#define ELE_DISABLED_FEATURE_FAILURE_IND (0xB6)
+#define ELE_MUST_ATTEST_FAILURE_IND (0xB7)
+#define ELE_RNG_NOT_STARTED_FAILURE_IND (0xB8)
+#define ELE_CRC_ERROR_IND (0xB9)
+#define ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND (0xBB)
+#define ELE_INCONSISTENT_PAR_FAILURE_IND (0xBC)
+#define ELE_RNG_INST_FAILURE_FAILURE_IND (0xBD)
+#define ELE_LOCKED_REG_FAILURE_IND (0xBE)
+#define ELE_BAD_ID_FAILURE_IND (0xBF)
+#define ELE_INVALID_OPERATION_FAILURE_IND (0xC0)
+#define ELE_NON_SECURE_STATE_FAILURE_IND (0xC1)
+#define ELE_MSG_TRUNCATED_IND (0xC2)
+#define ELE_BAD_IMAGE_NUM_FAILURE_IND (0xC3)
+#define ELE_BAD_IMAGE_ADDR_FAILURE_IND (0xC4)
+#define ELE_BAD_IMAGE_PARAM_FAILURE_IND (0xC5)
+#define ELE_BAD_IMAGE_TYPE_FAILURE_IND (0xC6)
+#define ELE_CORRUPTED_SRK_FAILURE_IND (0xD0)
+#define ELE_OUT_OF_MEMORY_IND (0xD1)
+#define ELE_CSTM_FAILURE_IND (0xCF)
+#define ELE_OLD_VERSION_FAILURE_IND (0xCE)
+#define ELE_WRONG_BOOT_MODE_FAILURE_IND (0xCD)
+#define ELE_APC_ALREADY_ENABLED_FAILURE_IND (0xCB)
+#define ELE_RTC_ALREADY_ENABLED_FAILURE_IND (0xCC)
+#define ELE_ABORT_IND (0xFF)
+
+/* ELE IPC identifier */
+#define ELE_IPC_MU_RTD (0x1)
+#define ELE_IPC_MU_APD (0x2)
+
+/* ELE Status*/
+#define ELE_SUCCESS_IND (0xD6)
+#define ELE_FAILURE_IND (0x29)
+
+#define S400_MAX_MSG 255U
+
+struct sentinel_msg {
+ u8 version;
+ u8 size;
+ u8 command;
+ u8 tag;
+ u32 data[(S400_MAX_MSG - 1U)];
+};
+
+struct sentinel_get_info_data{
+ u32 hdr;
+ u32 soc;
+ u32 lc;
+ u32 uid[4];
+ u32 sha256_rom_patch[8];
+ u32 sha_fw[8];
+};
+
+int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response);
+int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
+int ahab_release_container(u32 *response);
+int ahab_verify_image(u32 img_id, u32 *response);
+int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
+int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
+int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response);
+int ahab_release_caam(u32 core_did, u32 *response);
+int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
+int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
+int ahab_get_info(struct sentinel_get_info_data *info, u32 *response);
+int ahab_get_fw_status(u32 *status, u32 *response);
+int ahab_release_m33_trout(void);
+int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response);
+int ahab_start_rng(void);
+
+#endif
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 593a1cf404..57557db715 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -32,6 +32,7 @@ struct bd_info;
#define is_mx7() (is_soc_type(MXC_SOC_MX7))
#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
#define is_imx8() (is_soc_type(MXC_SOC_IMX8))
+#define is_imx9() (is_soc_type(MXC_SOC_IMX9))
#define is_imxrt() (is_soc_type(MXC_SOC_IMXRT))
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
@@ -83,6 +84,8 @@ struct bd_info;
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
#define is_imx8dxl() (is_cpu_type(MXC_CPU_IMX8DXL))
+#define is_imx93() (is_cpu_type(MXC_CPU_IMX93))
+
#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
#define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
@@ -151,7 +154,7 @@ struct rproc_att {
u32 size; /* size of reg range */
};
-#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP)
+#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP) || defined(CONFIG_IMX9)
struct rom_api {
u16 ver;
u16 tag;
@@ -172,6 +175,13 @@ enum boot_dev_type_e {
BT_DEV_TYPE_INVALID = 0xFF
};
+enum boot_stage_type {
+ BT_STAGE_PRIMARY = 0x6,
+ BT_STAGE_SECONDARY = 0x9,
+ BT_STAGE_RECOVERY = 0xa,
+ BT_STAGE_USB = 0x5,
+};
+
#define QUERY_ROM_VER 1
#define QUERY_BT_DEV 2
#define QUERY_PAGE_SZ 3
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index fecc0b6107..0616b05a05 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -229,7 +229,7 @@ config DDRMC_VF610_CALIBRATION
config SPL_IMX_ROMAPI_LOADADDR
hex "Default load address to load image through ROM API"
- depends on IMX8MN || IMX8MP || IMX8ULP
+ depends on IMX8MN || IMX8MP || IMX8ULP || IMX9
config IMX_DCD_ADDR
hex "DCD Blocks location on the image"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 6dc02efe2c..4ebf95d2b3 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -5,7 +5,7 @@
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m imx9 vf610))
obj-y = iomux-v3.o
endif
@@ -30,12 +30,12 @@ endif
obj-$(CONFIG_GPT_TIMER) += timer.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx7ulp imx8m imx8 imxrt imx8ulp))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx7ulp imx8m imx8 imxrt imx8ulp imx9))
obj-y += misc.o
obj-$(CONFIG_CMD_PRIBLOB) += priblob.o
obj-$(CONFIG_SPL_BUILD) += spl.o
endif
-ifeq ($(SOC),$(filter $(SOC),imx8m imx8 imx8ulp))
+ifeq ($(SOC),$(filter $(SOC),imx8m imx8 imx8ulp imx9))
obj-y += dt_optee.o
endif
ifeq ($(SOC),$(filter $(SOC),mx7))
@@ -89,6 +89,10 @@ ifeq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image-container.o parse-container.o
endif
+ifeq ($(SOC),$(filter $(SOC),imx8ulp imx9))
+obj-$(CONFIG_AHAB_BOOT) += ele_ahab.o
+endif
+
PLUGIN = board/$(BOARDDIR)/plugin
ifeq ($(CONFIG_USE_IMXIMG_PLUGIN),y)
@@ -292,6 +296,7 @@ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
obj-$(CONFIG_ARCH_IMX8ULP) += imx8ulp/
obj-$(CONFIG_IMX8M) += imx8m/
obj-$(CONFIG_ARCH_IMX8) += imx8/
+obj-$(CONFIG_ARCH_IMX9) += imx9/
obj-$(CONFIG_ARCH_IMXRT) += imxrt/
obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
new file mode 100644
index 0000000000..6daa7a96a0
--- /dev/null
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -0,0 +1,590 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/sys_proto.h>
+#include <asm/arch-imx/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/image.h>
+#include <console.h>
+#include <cpu_func.h>
+#include <asm/mach-imx/ahab.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xFFFFUL)
+
+#define AHAB_MAX_EVENTS 8
+
+static char *ele_ipc_str[] = {
+ "IPC = MU RTD (0x1)\n",
+ "IPC = MU APD (0x2)\n",
+ "IPC = INVALID\n",
+ NULL
+};
+
+static char *ele_status_str[] = {
+ "STA = ELE_SUCCESS_IND (0xD6)\n",
+ "STA = ELE_FAILURE_IND (0x29)\n",
+ "STA = INVALID\n",
+ NULL
+};
+
+static char *ele_cmd_str[] = {
+ "CMD = ELE_PING_REQ (0x01)\n",
+ "CMD = ELE_FW_AUTH_REQ (0x02)\n",
+ "CMD = ELE_RESTART_RST_TIMER_REQ (0x04)\n",
+ "CMD = ELE_DUMP_DEBUG_BUFFER_REQ (0x21)\n",
+ "CMD = ELE_OEM_CNTN_AUTH_REQ (0x87)\n",
+ "CMD = ELE_VERIFY_IMAGE_REQ (0x88)\n",
+ "CMD = ELE_RELEASE_CONTAINER_REQ (0x89)\n",
+ "CMD = ELE_WRITE_SECURE_FUSE_REQ (0x91)\n",
+ "CMD = ELE_FWD_LIFECYCLE_UP_REQ (0x95)\n",
+ "CMD = ELE_READ_FUSE_REQ (0x97)\n",
+ "CMD = ELE_GET_FW_VERSION_REQ (0x9D)\n",
+ "CMD = ELE_RET_LIFECYCLE_UP_REQ (0xA0)\n",
+ "CMD = ELE_GET_EVENTS_REQ (0xA2)\n",
+ "CMD = ELE_ENABLE_PATCH_REQ (0xC3)\n",
+ "CMD = ELE_RELEASE_RDC_REQ (0xC4)\n",
+ "CMD = ELE_GET_FW_STATUS_REQ (0xC5)\n",
+ "CMD = ELE_ENABLE_OTFAD_REQ (0xC6)\n",
+ "CMD = ELE_RESET_REQ (0xC7)\n",
+ "CMD = ELE_UPDATE_OTP_CLKDIV_REQ (0xD0)\n",
+ "CMD = ELE_POWER_DOWN_REQ (0xD1)\n",
+ "CMD = ELE_ENABLE_APC_REQ (0xD2)\n",
+ "CMD = ELE_ENABLE_RTC_REQ (0xD3)\n",
+ "CMD = ELE_DEEP_POWER_DOWN_REQ (0xD4)\n",
+ "CMD = ELE_STOP_RST_TIMER_REQ (0xD5)\n",
+ "CMD = ELE_WRITE_FUSE_REQ (0xD6)\n",
+ "CMD = ELE_RELEASE_CAAM_REQ (0xD7)\n",
+ "CMD = ELE_RESET_A35_CTX_REQ (0xD8)\n",
+ "CMD = ELE_MOVE_TO_UNSECURED_REQ (0xD9)\n",
+ "CMD = ELE_GET_INFO_REQ (0xDA)\n",
+ "CMD = ELE_ATTEST_REQ (0xDB)\n",
+ "CMD = ELE_RELEASE_PATCH_REQ (0xDC)\n",
+ "CMD = ELE_OTP_SEQ_SWITH_REQ (0xDD)\n",
+ "CMD = INVALID\n",
+ NULL
+};
+
+static char *ele_ind_str[] = {
+ "IND = ELE_ROM_PING_FAILURE_IND (0x0A)\n",
+ "IND = ELE_FW_PING_FAILURE_IND (0x1A)\n",
+ "IND = ELE_BAD_SIGNATURE_FAILURE_IND (0xF0)\n",
+ "IND = ELE_BAD_HASH_FAILURE_IND (0xF1)\n",
+ "IND = ELE_INVALID_LIFECYCLE_IND (0xF2)\n",
+ "IND = ELE_PERMISSION_DENIED_FAILURE_IND (0xF3)\n",
+ "IND = ELE_INVALID_MESSAGE_FAILURE_IND (0xF4)\n",
+ "IND = ELE_BAD_VALUE_FAILURE_IND (0xF5)\n",
+ "IND = ELE_BAD_FUSE_ID_FAILURE_IND (0xF6)\n",
+ "IND = ELE_BAD_CONTAINER_FAILURE_IND (0xF7)\n",
+ "IND = ELE_BAD_VERSION_FAILURE_IND (0xF8)\n",
+ "IND = ELE_INVALID_KEY_FAILURE_IND (0xF9)\n",
+ "IND = ELE_BAD_KEY_HASH_FAILURE_IND (0xFA)\n",
+ "IND = ELE_NO_VALID_CONTAINER_FAILURE_IND (0xFB)\n",
+ "IND = ELE_BAD_CERTIFICATE_FAILURE_IND (0xFC)\n",
+ "IND = ELE_BAD_UID_FAILURE_IND (0xFD)\n",
+ "IND = ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND (0xFE)\n",
+ "IND = ELE_MUST_SIGNED_FAILURE_IND (0xE0)\n",
+ "IND = ELE_NO_AUTHENTICATION_FAILURE_IND (0xEE)\n",
+ "IND = ELE_BAD_SRK_SET_FAILURE_IND (0xEF)\n",
+ "IND = ELE_UNALIGNED_PAYLOAD_FAILURE_IND (0xA6)\n",
+ "IND = ELE_WRONG_SIZE_FAILURE_IND (0xA7)\n",
+ "IND = ELE_ENCRYPTION_FAILURE_IND (0xA8)\n",
+ "IND = ELE_DECRYPTION_FAILURE_IND (0xA9)\n",
+ "IND = ELE_OTP_PROGFAIL_FAILURE_IND (0xAA)\n",
+ "IND = ELE_OTP_LOCKED_FAILURE_IND (0xAB)\n",
+ "IND = ELE_OTP_INVALID_IDX_FAILURE_IND (0xAD)\n",
+ "IND = ELE_TIME_OUT_FAILURE_IND (0xB0)\n",
+ "IND = ELE_BAD_PAYLOAD_FAILURE_IND (0xB1)\n",
+ "IND = ELE_WRONG_ADDRESS_FAILURE_IND (0xB4)\n",
+ "IND = ELE_DMA_FAILURE_IND (0xB5)\n",
+ "IND = ELE_DISABLED_FEATURE_FAILURE_IND (0xB6)\n",
+ "IND = ELE_MUST_ATTEST_FAILURE_IND (0xB7)\n",
+ "IND = ELE_RNG_NOT_STARTED_FAILURE_IND (0xB8)\n",
+ "IND = ELE_CRC_ERROR_IND (0xB9)\n",
+ "IND = ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND (0xBB)\n",
+ "IND = ELE_INCONSISTENT_PAR_FAILURE_IND (0xBC)\n",
+ "IND = ELE_RNG_INST_FAILURE_FAILURE_IND (0xBD)\n",
+ "IND = ELE_LOCKED_REG_FAILURE_IND (0xBE)\n",
+ "IND = ELE_BAD_ID_FAILURE_IND (0xBF)\n",
+ "IND = ELE_INVALID_OPERATION_FAILURE_IND (0xC0)\n",
+ "IND = ELE_NON_SECURE_STATE_FAILURE_IND (0xC1)\n",
+ "IND = ELE_MSG_TRUNCATED_IND (0xC2)\n",
+ "IND = ELE_BAD_IMAGE_NUM_FAILURE_IND (0xC3)\n",
+ "IND = ELE_BAD_IMAGE_ADDR_FAILURE_IND (0xC4)\n",
+ "IND = ELE_BAD_IMAGE_PARAM_FAILURE_IND (0xC5)\n",
+ "IND = ELE_BAD_IMAGE_TYPE_FAILURE_IND (0xC6)\n",
+ "IND = ELE_CORRUPTED_SRK_FAILURE_IND (0xD0)\n",
+ "IND = ELE_OUT_OF_MEMORY_IND (0xD1)\n",
+ "IND = ELE_CSTM_FAILURE_IND (0xCF)\n",
+ "IND = ELE_OLD_VERSION_FAILURE_IND (0xCE)\n",
+ "IND = ELE_WRONG_BOOT_MODE_FAILURE_IND (0xCD)\n",
+ "IND = ELE_APC_ALREADY_ENABLED_FAILURE_IND (0xCB)\n",
+ "IND = ELE_RTC_ALREADY_ENABLED_FAILURE_IND (0xCC)\n",
+ "IND = ELE_ABORT_IND (0xFF)\n",
+ "IND = INVALID\n",
+ NULL
+};
+
+static u8 ele_cmd[] = {
+ ELE_PING_REQ,
+ ELE_FW_AUTH_REQ,
+ ELE_RESTART_RST_TIMER_REQ,
+ ELE_DUMP_DEBUG_BUFFER_REQ,
+ ELE_OEM_CNTN_AUTH_REQ,
+ ELE_VERIFY_IMAGE_REQ,
+ ELE_RELEASE_CONTAINER_REQ,
+ ELE_WRITE_SECURE_FUSE_REQ,
+ ELE_FWD_LIFECYCLE_UP_REQ,
+ ELE_READ_FUSE_REQ,
+ ELE_GET_FW_VERSION_REQ,
+ ELE_RET_LIFECYCLE_UP_REQ,
+ ELE_GET_EVENTS_REQ,
+ ELE_ENABLE_PATCH_REQ,
+ ELE_RELEASE_RDC_REQ,
+ ELE_GET_FW_STATUS_REQ,
+ ELE_ENABLE_OTFAD_REQ,
+ ELE_RESET_REQ,
+ ELE_UPDATE_OTP_CLKDIV_REQ,
+ ELE_POWER_DOWN_REQ,
+ ELE_ENABLE_APC_REQ,
+ ELE_ENABLE_RTC_REQ,
+ ELE_DEEP_POWER_DOWN_REQ,
+ ELE_STOP_RST_TIMER_REQ,
+ ELE_WRITE_FUSE_REQ,
+ ELE_RELEASE_CAAM_REQ,
+ ELE_RESET_A35_CTX_REQ,
+ ELE_MOVE_TO_UNSECURED_REQ,
+ ELE_GET_INFO_REQ,
+ ELE_ATTEST_REQ,
+ ELE_RELEASE_PATCH_REQ,
+ ELE_OTP_SEQ_SWITH_REQ
+};
+
+static u8 ele_ind[] = {
+ ELE_ROM_PING_FAILURE_IND,
+ ELE_FW_PING_FAILURE_IND,
+ ELE_BAD_SIGNATURE_FAILURE_IND,
+ ELE_BAD_HASH_FAILURE_IND,
+ ELE_INVALID_LIFECYCLE_IND,
+ ELE_PERMISSION_DENIED_FAILURE_IND,
+ ELE_INVALID_MESSAGE_FAILURE_IND,
+ ELE_BAD_VALUE_FAILURE_IND,
+ ELE_BAD_FUSE_ID_FAILURE_IND,
+ ELE_BAD_CONTAINER_FAILURE_IND,
+ ELE_BAD_VERSION_FAILURE_IND,
+ ELE_INVALID_KEY_FAILURE_IND,
+ ELE_BAD_KEY_HASH_FAILURE_IND,
+ ELE_NO_VALID_CONTAINER_FAILURE_IND,
+ ELE_BAD_CERTIFICATE_FAILURE_IND,
+ ELE_BAD_UID_FAILURE_IND,
+ ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND,
+ ELE_MUST_SIGNED_FAILURE_IND,
+ ELE_NO_AUTHENTICATION_FAILURE_IND,
+ ELE_BAD_SRK_SET_FAILURE_IND,
+ ELE_UNALIGNED_PAYLOAD_FAILURE_IND,
+ ELE_WRONG_SIZE_FAILURE_IND,
+ ELE_ENCRYPTION_FAILURE_IND,
+ ELE_DECRYPTION_FAILURE_IND,
+ ELE_OTP_PROGFAIL_FAILURE_IND,
+ ELE_OTP_LOCKED_FAILURE_IND,
+ ELE_OTP_INVALID_IDX_FAILURE_IND,
+ ELE_TIME_OUT_FAILURE_IND,
+ ELE_BAD_PAYLOAD_FAILURE_IND,
+ ELE_WRONG_ADDRESS_FAILURE_IND,
+ ELE_DMA_FAILURE_IND,
+ ELE_DISABLED_FEATURE_FAILURE_IND,
+ ELE_MUST_ATTEST_FAILURE_IND,
+ ELE_RNG_NOT_STARTED_FAILURE_IND,
+ ELE_CRC_ERROR_IND,
+ ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND,
+ ELE_INCONSISTENT_PAR_FAILURE_IND,
+ ELE_RNG_INST_FAILURE_FAILURE_IND,
+ ELE_LOCKED_REG_FAILURE_IND,
+ ELE_BAD_ID_FAILURE_IND,
+ ELE_INVALID_OPERATION_FAILURE_IND,
+ ELE_NON_SECURE_STATE_FAILURE_IND,
+ ELE_MSG_TRUNCATED_IND,
+ ELE_BAD_IMAGE_NUM_FAILURE_IND,
+ ELE_BAD_IMAGE_ADDR_FAILURE_IND,
+ ELE_BAD_IMAGE_PARAM_FAILURE_IND,
+ ELE_BAD_IMAGE_TYPE_FAILURE_IND,
+ ELE_CORRUPTED_SRK_FAILURE_IND,
+ ELE_OUT_OF_MEMORY_IND,
+ ELE_CSTM_FAILURE_IND,
+ ELE_OLD_VERSION_FAILURE_IND,
+ ELE_WRONG_BOOT_MODE_FAILURE_IND,
+ ELE_APC_ALREADY_ENABLED_FAILURE_IND,
+ ELE_RTC_ALREADY_ENABLED_FAILURE_IND,
+ ELE_ABORT_IND
+};
+
+static u8 ele_ipc[] = {
+ ELE_IPC_MU_RTD,
+ ELE_IPC_MU_APD
+};
+
+static u8 ele_status[] = {
+ ELE_SUCCESS_IND,
+ ELE_FAILURE_IND
+};
+
+static inline u32 get_idx(u8 *list, u8 tgt, u32 size)
+{
+ u32 i;
+
+ for (i = 0; i < size; i++) {
+ if (list[i] == tgt)
+ return i;
+ }
+
+ return i; /* last str is invalid */
+}
+
+static void display_ahab_auth_ind(u32 event)
+{
+ u8 resp_ind = (event >> 8) & 0xff;
+
+ printf("%s\n", ele_ind_str[get_idx(ele_ind, resp_ind, ARRAY_SIZE(ele_ind))]);
+}
+
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
+{
+ int err;
+ u32 resp;
+ memcpy((void *)IMG_CONTAINER_BASE, (const void *)container,
+ ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
+
+ flush_dcache_range(IMG_CONTAINER_BASE,
+ IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1);
+
+ err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE,
+ &resp);
+ if (err) {
+ printf("Authenticate container hdr failed, return %d, resp 0x%x\n",
+ err, resp);
+ display_ahab_auth_ind(resp);
+ }
+
+ return err;
+}
+
+int ahab_auth_release(void)
+{
+ int err;
+ u32 resp;
+
+ err = ahab_release_container(&resp);
+ if (err) {
+ printf("Error: release container failed, resp 0x%x!\n", resp);
+ display_ahab_auth_ind(resp);
+ }
+
+ return err;
+}
+
+int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
+{
+ int err;
+ u32 resp;
+
+ err = ahab_verify_image(image_index, &resp);
+ if (err) {
+ printf("Authenticate img %d failed, return %d, resp 0x%x\n",
+ image_index, err, resp);
+ display_ahab_auth_ind(resp);
+
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static inline bool check_in_dram(ulong addr)
+{
+ int i;
+ struct bd_info *bd = gd->bd;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+ if (bd->bi_dram[i].size) {
+ if (addr >= bd->bi_dram[i].start &&
+ addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
+ return true;
+ }
+ }
+
+ return false;
+}
+
+int authenticate_os_container(ulong addr)
+{
+ struct container_hdr *phdr;
+ int i, ret = 0;
+ int err;
+ u16 length;
+ struct boot_img_t *img;
+ unsigned long s, e;
+
+ if (addr % 4) {
+ puts("Error: Image's address is not 4 byte aligned\n");
+ return -EINVAL;
+ }
+
+ if (!check_in_dram(addr)) {
+ puts("Error: Image's address is invalid\n");
+ return -EINVAL;
+ }
+
+ phdr = (struct container_hdr *)addr;
+ if (phdr->tag != 0x87 || phdr->version != 0x0) {
+ printf("Error: Wrong container header\n");
+ return -EFAULT;
+ }
+
+ if (!phdr->num_images) {
+ printf("Error: Wrong container, no image found\n");
+ return -EFAULT;
+ }
+
+ length = phdr->length_lsb + (phdr->length_msb << 8);
+
+ debug("container length %u\n", length);
+
+ err = ahab_auth_cntr_hdr(phdr, length);
+ if (err) {
+ ret = -EIO;
+ goto exit;
+ }
+
+ debug("Verify images\n");
+
+ /* Copy images to dest address */
+ for (i = 0; i < phdr->num_images; i++) {
+ img = (struct boot_img_t *)(addr +
+ sizeof(struct container_hdr) +
+ i * sizeof(struct boot_img_t));
+
+ debug("img %d, dst 0x%x, src 0x%lx, size 0x%x\n",
+ i, (uint32_t) img->dst, img->offset + addr, img->size);
+
+ memcpy((void *)img->dst, (const void *)(img->offset + addr),
+ img->size);
+
+ s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1;
+
+ flush_dcache_range(s, e);
+
+ ret = ahab_verify_cntr_image(img, i);
+ if (ret)
+ goto exit;
+ }
+
+exit:
+ debug("ahab_auth_release, 0x%x\n", ret);
+ ahab_auth_release();
+
+ return ret;
+}
+
+static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong addr;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ printf("Authenticate OS container at 0x%lx\n", addr);
+
+ if (authenticate_os_container(addr))
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+static void display_life_cycle(u32 lc)
+{
+ printf("Lifecycle: 0x%08X, ", lc);
+ switch (lc) {
+ case 0x1:
+ printf("BLANK\n\n");
+ break;
+ case 0x2:
+ printf("FAB\n\n");
+ break;
+ case 0x4:
+ printf("NXP Provisioned\n\n");
+ break;
+ case 0x8:
+ printf("OEM Open\n\n");
+ break;
+ case 0x20:
+ printf("OEM closed\n\n");
+ break;
+ case 0x40:
+ printf("Field Return OEM\n\n");
+ break;
+ case 0x80:
+ printf("Field Return NXP\n\n");
+ break;
+ case 0x100:
+ printf("OEM Locked\n\n");
+ break;
+ case 0x200:
+ printf("BRICKED\n\n");
+ break;
+ default:
+ printf("Unknown\n\n");
+ break;
+ }
+}
+
+static int confirm_close(void)
+{
+ puts("Warning: Please ensure your sample is in NXP closed state, "
+ "OEM SRK hash has been fused, \n"
+ " and you are able to boot a signed image successfully "
+ "without any SECO events reported.\n"
+ " If not, your sample will be unrecoverable.\n"
+ "\nReally perform this operation? <y/N>\n");
+
+ if (confirm_yesno())
+ return 1;
+
+ puts("Ahab close aborted\n");
+ return 0;
+}
+
+static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int err;
+ u32 resp;
+ u32 lc;
+
+ if (!confirm_close())
+ return -EACCES;
+
+ lc = readl(FSB_BASE_ADDR + 0x41c);
+ lc &= 0x3ff;
+
+ if (lc != 0x8) {
+ puts("Current lifecycle is NOT OEM open, can't move to OEM closed\n");
+ display_life_cycle(lc);
+ return -EPERM;
+ }
+
+ err = ahab_forward_lifecycle(8, &resp);
+ if (err != 0) {
+ printf("Error in forward lifecycle to OEM closed\n");
+ return -EIO;
+ }
+
+ printf("Change to OEM closed successfully\n");
+
+ return 0;
+}
+
+int ahab_dump(void)
+{
+ u32 buffer[32];
+ int ret, i = 0;
+
+ do {
+ ret = ahab_dump_buffer(buffer, 32);
+ if (ret < 0) {
+ printf("Error in dump AHAB log\n");
+ return -EIO;
+ }
+
+ if (ret == 1) {
+ break;
+ } else {
+ for (i = 0; i < ret; i++)
+ printf("0x%x\n", buffer[i]);
+ }
+ } while (ret >= 21);
+
+ return 0;
+}
+
+static int do_ahab_dump(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ return ahab_dump();
+}
+
+static void display_event(u32 event)
+{
+ printf("\n\t0x%08x\n", event);
+ printf("\t%s", ele_ipc_str[get_idx(ele_ipc,
+ (event >> 24) & 0xFF, ARRAY_SIZE(ele_ipc))]);
+ printf("\t%s", ele_cmd_str[get_idx(ele_cmd,
+ (event >> 16) & 0xFF, ARRAY_SIZE(ele_cmd))]);
+ printf("\t%s", ele_ind_str[get_idx(ele_ind,
+ (event >> 8) & 0xFF, ARRAY_SIZE(ele_ind))]);
+ printf("\t%s", ele_status_str[get_idx(ele_status,
+ event & 0xFF, ARRAY_SIZE(ele_status))]);
+}
+
+static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ u32 lc, i;
+ u32 events[AHAB_MAX_EVENTS];
+ u32 cnt = AHAB_MAX_EVENTS;
+ int ret;
+
+ lc = readl(FSB_BASE_ADDR + 0x41c);
+ lc &= 0x3ff;
+
+ display_life_cycle(lc);
+
+ ret = ahab_get_events(events, &cnt, NULL);
+ if (ret) {
+ printf("Get ELE EVENTS error %d\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ if (!cnt) {
+ puts("\n\tNo Events Found!\n");
+ return 0;
+ }
+
+ for (i = 0; i < cnt; i++)
+ display_event(events[i]);
+
+ return 0;
+}
+
+U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
+ "autenticate OS container via AHAB",
+ "addr\n"
+ "addr - OS container hex address\n"
+);
+
+U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close,
+ "Change AHAB lifecycle to OEM closed",
+ ""
+);
+
+U_BOOT_CMD(ahab_dump, CONFIG_SYS_MAXARGS, 1, do_ahab_dump,
+ "Dump AHAB log for debug",
+ ""
+);
+
+U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status,
+ "display AHAB lifecycle only",
+ ""
+);
diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c
index b857a48da1..367410b154 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -191,39 +191,41 @@ static unsigned long get_boot_device_offset(void *dev, int dev_type)
unsigned long offset = 0, sec_set_off = 0;
bool sec_boot = false;
- sec_boot = check_secondary_cnt_set(&sec_set_off);
- if (sec_boot)
- printf("Secondary set selected\n");
- else
- printf("Primary set selected\n");
-
- if (dev_type == MMC_DEV) {
- struct mmc *mmc = (struct mmc *)dev;
+ if (dev_type == ROM_API_DEV) {
+ offset = (unsigned long)dev;
+ } else {
+ sec_boot = check_secondary_cnt_set(&sec_set_off);
+ if (sec_boot)
+ printf("Secondary set selected\n");
+ else
+ printf("Primary set selected\n");
- if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) {
- offset = sec_boot? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET;
- } else {
- u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
+ if (dev_type == MMC_DEV) {
+ struct mmc *mmc = (struct mmc *)dev;
- if (part == 1 || part == 2) {
- if (is_imx8qxp() && is_soc_rev(CHIP_REV_B))
- offset = CONTAINER_HDR_MMCSD_OFFSET;
- else
- offset = CONTAINER_HDR_EMMC_OFFSET;
- } else {
+ if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) {
offset = sec_boot? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET;
+ } else {
+ u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
+
+ if (part == 1 || part == 2) {
+ if (is_imx8qxp() && is_soc_rev(CHIP_REV_B))
+ offset = CONTAINER_HDR_MMCSD_OFFSET;
+ else
+ offset = CONTAINER_HDR_EMMC_OFFSET;
+ } else {
+ offset = sec_boot? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET;
+ }
}
+ } else if (dev_type == QSPI_DEV) {
+ offset = sec_boot? (sec_set_off + CONTAINER_HDR_QSPI_OFFSET) : CONTAINER_HDR_QSPI_OFFSET;
+ } else if (dev_type == NAND_DEV) {
+ offset = sec_boot? (sec_set_off + CONTAINER_HDR_NAND_OFFSET) : CONTAINER_HDR_NAND_OFFSET;
+ } else if (dev_type == QSPI_NOR_DEV) {
+ offset = CONTAINER_HDR_QSPI_OFFSET + 0x08000000;
+ } else if (dev_type == RAM_DEV) {
+ offset = (unsigned long)dev + CONTAINER_HDR_MMCSD_OFFSET;
}
- } else if (dev_type == QSPI_DEV) {
- offset = sec_boot? (sec_set_off + CONTAINER_HDR_QSPI_OFFSET) : CONTAINER_HDR_QSPI_OFFSET;
- } else if (dev_type == NAND_DEV) {
- offset = sec_boot? (sec_set_off + CONTAINER_HDR_NAND_OFFSET) : CONTAINER_HDR_NAND_OFFSET;
- } else if (dev_type == QSPI_NOR_DEV) {
- offset = CONTAINER_HDR_QSPI_OFFSET + 0x08000000;
- } else if (dev_type == ROM_API_DEV) {
- offset = (unsigned long)dev;
- } else if (dev_type == RAM_DEV) {
- offset = (unsigned long)dev + CONTAINER_HDR_MMCSD_OFFSET;
}
debug("container set offset 0x%lx\n", offset);
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 456073873d..a225a9784f 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -120,6 +120,24 @@ config TARGET_IMX8MM_DDR4_EVK
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+config TARGET_IMX8MM_AB2
+ bool "imx8mm LPDDR4 Audio board 2.0"
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+ select FSL_CAAM
+ select FSL_BLOB
+ select SPL_CRYPTO if SPL
+
+config TARGET_IMX8MM_DDR4_AB2
+ bool "imx8mm DDR4 Audio board 2.0"
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_DDR4
+ select FSL_CAAM
+ select FSL_BLOB
+ select SPL_CRYPTO if SPL
+
config TARGET_IMX8MM_ICORE_MX8MM
bool "Engicam i.Core MX8M Mini SOM"
select IMX8MM
@@ -179,6 +197,33 @@ config TARGET_IMX8MN_DDR3_EVK
select FSL_BLOB
select SPL_CRYPTO if SPL
+config TARGET_IMX8MN_AB2
+ bool "imx8mn LPDDR4 Audio board 2.0"
+ select IMX8MN
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+ select FSL_CAAM
+ select FSL_BLOB
+ select SPL_CRYPTO if SPL
+
+config TARGET_IMX8MN_DDR4_AB2
+ bool "imx8mn DDR4 Audio board 2.0"
+ select IMX8MN
+ select SUPPORT_SPL
+ select IMX8M_DDR4
+ select FSL_CAAM
+ select FSL_BLOB
+ select SPL_CRYPTO if SPL
+
+config TARGET_IMX8MN_DDR3L_AB2
+ bool "imx8mn DDR3L Audio board 2.0"
+ select IMX8MN
+ select SUPPORT_SPL
+ select IMX8M_DDR3L
+ select FSL_CAAM
+ select FSL_BLOB
+ select SPL_CRYPTO if SPL
+
config TARGET_IMX8MN_VENICE
bool "Support Gateworks Venice iMX8M Nano module"
select BINMAN
@@ -305,6 +350,7 @@ source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
source "board/engicam/imx8mm/Kconfig"
source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mq_val/Kconfig"
+source "board/freescale/imx8mm_ab2/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
source "board/freescale/imx8mm_val/Kconfig"
source "board/freescale/imx8mn_evk/Kconfig"
diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig
index 1e465ab720..e82347ed68 100644
--- a/arch/arm/mach-imx/imx8ulp/Kconfig
+++ b/arch/arm/mach-imx/imx8ulp/Kconfig
@@ -40,12 +40,22 @@ config TARGET_IMX8ULP_9X9_EVK
select IMX8ULP_DRAM
select FSL_CAAM
select FSL_BLOB
- select MISC
select ARCH_MISC_INIT
select SPL_CRYPTO_SUPPORT if SPL
+config TARGET_IMX8ULP_WATCH
+ bool "imx8ulp_watch"
+ select IMX8ULP
+ select SUPPORT_SPL
+ select IMX8ULP_DRAM
+ select FSL_CAAM
+ select FSL_BLOB
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
+
endchoice
source "board/freescale/imx8ulp_evk/Kconfig"
+source "board/freescale/imx8ulp_watch/Kconfig"
endif
diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile
index f7692cf3a7..2c9938fcdf 100644
--- a/arch/arm/mach-imx/imx8ulp/Makefile
+++ b/arch/arm/mach-imx/imx8ulp/Makefile
@@ -5,7 +5,6 @@
obj-y += lowlevel_init.o
obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o
-obj-$(CONFIG_AHAB_BOOT) += ahab.o
ifeq ($(CONFIG_SPL_BUILD),y)
obj-y += upower/
diff --git a/arch/arm/mach-imx/imx8ulp/ahab.c b/arch/arm/mach-imx/imx8ulp/ahab.c
deleted file mode 100644
index 93957f74e0..0000000000
--- a/arch/arm/mach-imx/imx8ulp/ahab.c
+++ /dev/null
@@ -1,349 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/s400_api.h>
-#include <asm/mach-imx/sys_proto.h>
-#include <asm/arch-imx/cpu.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-imx/image.h>
-#include <console.h>
-#include <cpu_func.h>
-#include <asm/mach-imx/ahab.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define IMG_CONTAINER_BASE (0x22010000UL)
-#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xFFFFUL)
-
-#define AHAB_NO_AUTHENTICATION_IND 0xee
-#define AHAB_BAD_KEY_HASH_IND 0xfa
-#define AHAB_INVALID_KEY_IND 0xf9
-#define AHAB_BAD_SIGNATURE_IND 0xf0
-#define AHAB_BAD_HASH_IND 0xf1
-
-static void display_ahab_auth_ind(u32 event)
-{
- u8 resp_ind = (event >> 8) & 0xff;
-
- switch (resp_ind) {
- case AHAB_NO_AUTHENTICATION_IND:
- printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind);
- break;
- case AHAB_BAD_KEY_HASH_IND:
- printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind);
- break;
- case AHAB_INVALID_KEY_IND:
- printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind);
- break;
- case AHAB_BAD_SIGNATURE_IND:
- printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind);
- break;
- case AHAB_BAD_HASH_IND:
- printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind);
- break;
- default:
- printf("Unknown Indicator (0x%02X)\n\n", resp_ind);
- break;
- }
-}
-
-int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
-{
- int err;
- u32 resp;
- memcpy((void *)IMG_CONTAINER_BASE, (const void *)container,
- ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
-
- flush_dcache_range(IMG_CONTAINER_BASE,
- IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1);
-
- err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE,
- &resp);
- if (err) {
- printf("Authenticate container hdr failed, return %d, resp 0x%x\n",
- err, resp);
- display_ahab_auth_ind(resp);
- }
-
- return err;
-}
-
-int ahab_auth_release(void)
-{
- int err;
- u32 resp;
-
- err = ahab_release_container(&resp);
- if (err) {
- printf("Error: release container failed, resp 0x%x!\n", resp);
- display_ahab_auth_ind(resp);
- }
-
- return err;
-}
-
-int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
-{
- int err;
- u32 resp;
-
- err = ahab_verify_image(image_index, &resp);
- if (err) {
- printf("Authenticate img %d failed, return %d, resp 0x%x\n",
- image_index, err, resp);
- display_ahab_auth_ind(resp);
- return -EIO;
- }
-
- return 0;
-}
-
-static inline bool check_in_dram(ulong addr)
-{
- int i;
- struct bd_info *bd = gd->bd;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
- if (bd->bi_dram[i].size) {
- if (addr >= bd->bi_dram[i].start &&
- addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
- return true;
- }
- }
-
- return false;
-}
-
-int authenticate_os_container(ulong addr)
-{
- struct container_hdr *phdr;
- int i, ret = 0;
- int err;
- u16 length;
- struct boot_img_t *img;
- unsigned long s, e;
-
- if (addr % 4) {
- puts("Error: Image's address is not 4 byte aligned\n");
- return -EINVAL;
- }
-
- if (!check_in_dram(addr)) {
- puts("Error: Image's address is invalid\n");
- return -EINVAL;
- }
-
- phdr = (struct container_hdr *)addr;
- if (phdr->tag != 0x87 || phdr->version != 0x0) {
- printf("Error: Wrong container header\n");
- return -EFAULT;
- }
-
- if (!phdr->num_images) {
- printf("Error: Wrong container, no image found\n");
- return -EFAULT;
- }
-
- length = phdr->length_lsb + (phdr->length_msb << 8);
-
- debug("container length %u\n", length);
-
- err = ahab_auth_cntr_hdr(phdr, length);
- if (err) {
- ret = -EIO;
- goto exit;
- }
-
- debug("Verify images\n");
-
- /* Copy images to dest address */
- for (i = 0; i < phdr->num_images; i++) {
- img = (struct boot_img_t *)(addr +
- sizeof(struct container_hdr) +
- i * sizeof(struct boot_img_t));
-
- debug("img %d, dst 0x%x, src 0x%lx, size 0x%x\n",
- i, (uint32_t) img->dst, img->offset + addr, img->size);
-
- memcpy((void *)img->dst, (const void *)(img->offset + addr),
- img->size);
-
- s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
- e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1;
-
- flush_dcache_range(s, e);
-
- ret = ahab_verify_cntr_image(img, i);
- if (ret)
- goto exit;
- }
-
-exit:
- debug("ahab_auth_release, 0x%x\n", ret);
- ahab_auth_release();
-
- return ret;
-}
-
-static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- ulong addr;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- addr = simple_strtoul(argv[1], NULL, 16);
-
- printf("Authenticate OS container at 0x%lx\n", addr);
-
- if (authenticate_os_container(addr))
- return CMD_RET_FAILURE;
-
- return CMD_RET_SUCCESS;
-}
-
-static void display_life_cycle(u32 lc)
-{
- printf("Lifecycle: 0x%08X, ", lc);
- switch (lc) {
- case 0x1:
- printf("BLANK\n\n");
- break;
- case 0x2:
- printf("FAB\n\n");
- break;
- case 0x4:
- printf("NXP Provisioned\n\n");
- break;
- case 0x8:
- printf("OEM Open\n\n");
- break;
- case 0x10:
- printf("OEM Secure World Closed\n\n");
- break;
- case 0x20:
- printf("OEM closed\n\n");
- break;
- case 0x40:
- printf("Field Return OEM\n\n");
- break;
- case 0x80:
- printf("Field Return NXP\n\n");
- break;
- case 0x100:
- printf("OEM Locked\n\n");
- break;
- case 0x200:
- printf("BRICKED\n\n");
- break;
- default:
- printf("Unknown\n\n");
- break;
- }
-}
-
-static int confirm_close(void)
-{
- puts("Warning: Please ensure your sample is in NXP closed state, "
- "OEM SRK hash has been fused, \n"
- " and you are able to boot a signed image successfully "
- "without any SECO events reported.\n"
- " If not, your sample will be unrecoverable.\n"
- "\nReally perform this operation? <y/N>\n");
-
- if (confirm_yesno())
- return 1;
-
- puts("Ahab close aborted\n");
- return 0;
-}
-
-static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- int err;
- u32 resp;
-
- if (!confirm_close())
- return -EACCES;
-
- err = ahab_forward_lifecycle(8, &resp);
- if (err != 0) {
- printf("Error in forward lifecycle to OEM closed\n");
- return -EIO;
- }
-
- printf("Change to OEM closed successfully\n");
-
- return 0;
-}
-
-int ahab_dump(void)
-{
- u32 buffer[32];
- int ret, i = 0;
-
- do {
- ret = ahab_dump_buffer(buffer, 32);
- if (ret < 0) {
- printf("Error in dump AHAB log\n");
- return -EIO;
- }
-
- if (ret == 1) {
- break;
- } else {
- for (i = 0; i < ret; i++)
- printf("0x%x\n", buffer[i]);
- }
- } while (ret >= 21);
-
- return 0;
-}
-
-static int do_ahab_dump(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- return ahab_dump();
-}
-
-static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- u32 lc;
-
- lc = readl(FSB_BASE_ADDR + 0x41c);
- lc &= 0x3ff;
-
- display_life_cycle(lc);
- return 0;
-}
-
-U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
- "autenticate OS container via AHAB",
- "addr\n"
- "addr - OS container hex address\n"
-);
-
-U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close,
- "Change AHAB lifecycle to OEM closed",
- ""
-);
-
-U_BOOT_CMD(ahab_dump, CONFIG_SYS_MAXARGS, 1, do_ahab_dump,
- "Dump AHAB log for debug",
- ""
-);
-
-U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status,
- "display AHAB lifecycle only",
- ""
-);
diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c
index 3913b17051..d3c0e64cd6 100644
--- a/arch/arm/mach-imx/imx8ulp/cgc.c
+++ b/arch/arm/mach-imx/imx8ulp/cgc.c
@@ -169,6 +169,9 @@ void cgc1_pll3_init(ulong freq)
while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(30)))
;
+ clrbits_le32(&cgc1_regs->pll3div_pfd0, 0x3f3f3f3f);
+ clrbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f);
+
clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7));
clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(15));
clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(23));
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index b4240c83a1..2898c8b96c 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -447,10 +447,9 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz)
debug("PLL4 rate %ukhz\n", pll4_rate);
for (pfd = 12; pfd <= 35; pfd++) {
- parent_rate = pll4_rate;
- parent_rate = parent_rate * 18 / pfd;
-
for (div = 1; div <= 64; div++) {
+ parent_rate = pll4_rate;
+ parent_rate = parent_rate * 18 / pfd;
parent_rate = parent_rate / div;
for (pcd = 0; pcd < 8; pcd++) {
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index e2eca0633e..f5423ec7b9 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -8,8 +8,8 @@
#include <asm/types.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/mu_hal.h>
-#include <asm/arch/s400_api.h>
+#include <asm/mach-imx/mu_hal.h>
+#include <asm/mach-imx/s400_api.h>
#include <asm/arch/rdc.h>
#include <div64.h>
@@ -184,14 +184,14 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm)
int release_rdc(enum rdc_type type)
{
ulong s_mu_base = 0x27020000UL;
- struct imx8ulp_s400_msg msg;
+ struct sentinel_msg msg;
int ret;
u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
- msg.command = AHAB_RELEASE_RDC_REQ_CID;
+ msg.command = ELE_RELEASE_RDC_REQ;
msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */
mu_hal_init(s_mu_base);
@@ -276,6 +276,36 @@ void xrdc_init_mda(void)
void xrdc_init_mrc(void)
{
+ /* Re-config MRC3 for SRAM0 in case protected by S400 */
+ xrdc_config_mrc_w0_w1(3, 0, 0x22010000, 0x10000);
+ xrdc_config_mrc_dx_perm(3, 0, 0, 1);
+ xrdc_config_mrc_dx_perm(3, 0, 1, 1);
+ xrdc_config_mrc_dx_perm(3, 0, 4, 1);
+ xrdc_config_mrc_dx_perm(3, 0, 5, 1);
+ xrdc_config_mrc_dx_perm(3, 0, 6, 1);
+ xrdc_config_mrc_dx_perm(3, 0, 7, 1);
+ xrdc_config_mrc_w3_w4(3, 0, 0x0, 0x80000FFF);
+
+ /* Clear other 3 regions of MRC3 to invalid */
+ xrdc_config_mrc_w3_w4(3, 1, 0x0, 0x0);
+ xrdc_config_mrc_w3_w4(3, 2, 0x0, 0x0);
+ xrdc_config_mrc_w3_w4(3, 3, 0x0, 0x0);
+
+ /* Set MRC4 and MRC5 for DDR access from A35 and AP NIC PER masters */
+ xrdc_config_mrc_w0_w1(4, 0, CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
+ xrdc_config_mrc_dx_perm(4, 0, 1, 1);
+ xrdc_config_mrc_dx_perm(4, 0, 7, 1);
+ xrdc_config_mrc_w3_w4(4, 0, 0x0, 0x80000FFF);
+
+ xrdc_config_mrc_w0_w1(5, 0, CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
+ xrdc_config_mrc_dx_perm(5, 0, 1, 1);
+ xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF);
+
+ /* Set MRC6 for DDR access from Sentinel */
+ xrdc_config_mrc_w0_w1(6, 0, CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
+ xrdc_config_mrc_dx_perm(6, 0, 4, 1);
+ xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF);
+
/* The MRC8 is for SRAM1 */
xrdc_config_mrc_w0_w1(8, 0, 0x21000000, 0x10000);
/* Allow for all domains: So domain 2/3 (HIFI DSP/LPAV) is ok to access */
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index dc1fa70e3c..6e20b11801 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -13,8 +13,8 @@
#include <efi_loader.h>
#include <spl.h>
#include <asm/arch/rdc.h>
-#include <asm/arch/s400_api.h>
-#include <asm/arch/mu_hal.h>
+#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/mu_hal.h>
#include <cpu_func.h>
#include <asm/setup.h>
#include <dm.h>
@@ -152,9 +152,18 @@ int board_usb_gadget_port_auto(void)
}
#endif
+static void set_cpu_info(struct sentinel_get_info_data *info)
+{
+ gd->arch.soc_rev = info->soc;
+ gd->arch.lifecycle = info->lc;
+ memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32));
+}
+
u32 get_cpu_rev(void)
{
- return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0;
+ u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
+
+ return (MXC_CPU_IMX8ULP << 12) | (CHIP_REV_1_0 + rev);
}
enum bt_mode get_boot_mode(void)
@@ -177,14 +186,70 @@ enum bt_mode get_boot_mode(void)
bool m33_image_booted(void)
{
- u32 gp6 = 0;
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ u32 gp6 = 0;
+
+ /* DGO_GP6 */
+ gp6 = readl(SIM_SEC_BASE_ADDR + 0x28);
+ if (gp6 & (1 << 5))
+ return true;
+
+ return false;
+ } else {
+ u32 gpr0 = readl(SIM1_BASE_ADDR);
+ if (gpr0 & 0x1)
+ return true;
+
+ return false;
+ }
+}
+
+bool rdc_enabled_in_boot(void)
+{
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ u32 val = 0;
+ int ret;
+ bool rdc_en = true; /* Default assume DBD_EN is set */
- /* DGO_GP6 */
- gp6 = readl(SIM_SEC_BASE_ADDR + 0x28);
- if (gp6 & (1 << 5))
- return true;
+ /* Read DBD_EN fuse */
+ ret = fuse_read(8, 1, &val);
+ if (!ret)
+ rdc_en = !!(val & 0x200); /* only A1 part uses DBD_EN, so check DBD_EN new place*/
+
+ return rdc_en;
+ } else {
+ u32 gpr0 = readl(SIM1_BASE_ADDR);
+ if (gpr0 & 0x2)
+ return true;
+
+ return false;
+ }
+}
+
+static void spl_pass_boot_info(void)
+{
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ bool m33_booted = m33_image_booted();
+ bool rdc_en = rdc_enabled_in_boot();
+ u32 val = 0;
+
+ if (m33_booted)
+ val |= 0x1;
+
+ if (rdc_en)
+ val |= 0x2;
+
+ writel(val, SIM1_BASE_ADDR);
+ }
+}
- return false;
+bool is_m33_handshake_necessary(void)
+{
+ /* Only need handshake in u-boot */
+ if (!IS_ENABLED(CONFIG_SPL_BUILD))
+ return (m33_image_booted() || rdc_enabled_in_boot());
+ else
+ return false;
}
int m33_image_handshake(ulong timeout_ms)
@@ -290,7 +355,7 @@ int print_cpuinfo(void)
(cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
-#if defined(CONFIG_IMX_PMC_TEMPERATURE)
+#if defined(CONFIG_SCMI_THERMAL)
struct udevice *udev;
int ret, temp;
@@ -632,33 +697,65 @@ static void set_core0_reset_vector(u32 entry)
setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26));
}
-static int trdc_set_access(void)
+/* Not used now */
+int trdc_set_access(void)
{
/*
* TRDC mgr + 4 MBC + 2 MRC.
- * S400 should already configure when release RDC
- * A35 only map non-secure region for pbridge0 and 1, set sec_access to false
*/
- trdc_mbc_set_access(2, 7, 0, 49, false);
- trdc_mbc_set_access(2, 7, 0, 50, false);
- trdc_mbc_set_access(2, 7, 0, 51, false);
- trdc_mbc_set_access(2, 7, 0, 52, false);
- trdc_mbc_set_access(2, 7, 0, 53, false);
- trdc_mbc_set_access(2, 7, 0, 54, false);
-
- /* CGC0: PBridge0 slot 47 */
+ trdc_mbc_set_access(2, 7, 0, 49, true);
+ trdc_mbc_set_access(2, 7, 0, 50, true);
+ trdc_mbc_set_access(2, 7, 0, 51, true);
+ trdc_mbc_set_access(2, 7, 0, 52, true);
+ trdc_mbc_set_access(2, 7, 0, 53, true);
+ trdc_mbc_set_access(2, 7, 0, 54, true);
+
+ /* 0x1fff8000 used for resource table by remoteproc */
+ trdc_mbc_set_access(0, 7, 2, 31, false);
+
+ /* CGC0: PBridge0 slot 47 and PCC0 slot 48 */
trdc_mbc_set_access(2, 7, 0, 47, false);
+ trdc_mbc_set_access(2, 7, 0, 48, false);
+
+ /* PCC1 */
+ trdc_mbc_set_access(2, 7, 1, 17, false);
+ trdc_mbc_set_access(2, 7, 1, 34, false);
/* Iomuxc0: : PBridge1 slot 33 */
trdc_mbc_set_access(2, 7, 1, 33, false);
/* flexspi0 */
+ trdc_mbc_set_access(2, 7, 0, 57, false);
trdc_mrc_region_set_access(0, 7, 0x04000000, 0x0c000000, false);
/* tpm0: PBridge1 slot 21 */
trdc_mbc_set_access(2, 7, 1, 21, false);
/* lpi2c0: PBridge1 slot 24 */
trdc_mbc_set_access(2, 7, 1, 24, false);
+
+ /* Allow M33 to access TRDC MGR */
+ trdc_mbc_set_access(2, 6, 0, 49, true);
+ trdc_mbc_set_access(2, 6, 0, 50, true);
+ trdc_mbc_set_access(2, 6, 0, 51, true);
+ trdc_mbc_set_access(2, 6, 0, 52, true);
+ trdc_mbc_set_access(2, 6, 0, 53, true);
+ trdc_mbc_set_access(2, 6, 0, 54, true);
+
+ /* Set SAI0 for eDMA 0, NS */
+ trdc_mbc_set_access(2, 0, 1, 28, false);
+
+ /* Set SSRAM for eDMA0 access */
+ trdc_mbc_set_access(0, 0, 2, 0, false);
+ trdc_mbc_set_access(0, 0, 2, 1, false);
+ trdc_mbc_set_access(0, 0, 2, 2, false);
+ trdc_mbc_set_access(0, 0, 2, 3, false);
+ trdc_mbc_set_access(0, 0, 2, 4, false);
+ trdc_mbc_set_access(0, 0, 2, 5, false);
+ trdc_mbc_set_access(0, 0, 2, 6, false);
+ trdc_mbc_set_access(0, 0, 2, 7, false);
+
+ writel(0x800000a0, 0x28031840);
+
return 0;
}
@@ -705,10 +802,6 @@ void set_lpav_qos(void)
int arch_cpu_init(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
- u32 val = 0;
- int ret;
- bool rdc_en = true; /* Default assume DBD_EN is set */
-
/* Enable System Reset Interrupt using WDOG_AD */
setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13));
/* Clear AD_PERIPH Power switch domain out of reset interrupt flag */
@@ -725,29 +818,21 @@ int arch_cpu_init(void)
/* Disable wdog */
init_wdog();
- /* Read DBD_EN fuse */
- ret = fuse_read(8, 1, &val);
- if (!ret)
- rdc_en = !!(val & 0x4000);
-
if (get_boot_mode() == SINGLE_BOOT) {
- if (rdc_en)
- release_rdc(RDC_TRDC);
-
- trdc_set_access();
-
lpav_configure(false);
} else {
lpav_configure(true);
}
/* Release xrdc, then allow A35 to write SRAM2 */
- if (rdc_en)
+ if (rdc_enabled_in_boot())
release_rdc(RDC_XRDC);
xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00);
clock_init_early();
+
+ spl_pass_boot_info();
} else {
/* reconfigure core0 reset vector to ROM */
set_core0_reset_vector(0x1000);
@@ -756,10 +841,36 @@ int arch_cpu_init(void)
return 0;
}
+int checkcpu(void)
+{
+ if (is_m33_handshake_necessary()) {
+ if (!gd->arch.m33_handshake_done) {
+ puts("M33 Sync: Timeout, Boot Stop!\n");
+ hang();
+ } else {
+ puts("M33 Sync: OK\n");
+ }
+ }
+ return 0;
+}
+
int arch_cpu_init_dm(void)
{
struct udevice *devp;
int node, ret;
+ u32 res;
+ struct sentinel_get_info_data info;
+
+ if (!IS_ENABLED(CONFIG_SPL_BUILD) && is_m33_handshake_necessary()) {
+ /* Start handshake with M33 to ensure TRDC configuration completed */
+ ret = m33_image_handshake(1000);
+ if (!ret) {
+ gd->arch.m33_handshake_done = true;
+ } else {
+ gd->arch.m33_handshake_done = false;
+ return 0; /* Skip and go through to panic in checkcpu as console is ready then */
+ }
+ }
node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8ulp-mu");
@@ -769,6 +880,16 @@ int arch_cpu_init_dm(void)
return ret;
}
+ ret = ahab_get_info(&info, &res);
+ if (ret) {
+ printf("ahab_get_info failed %d\n", ret);
+ /* fallback to A0.1 revision */
+ memset((void *)&info, 0, sizeof(struct sentinel_get_info_data));
+ info.soc = 0xa000084d;
+ }
+
+ set_cpu_info(&info);
+
return 0;
}
@@ -856,7 +977,8 @@ int (*card_emmc_is_boot_part_en)(void) = (void *)0x67cc;
u32 spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev)
{
/* Hard code for eMMC image_offset on 8ULP ROM, need fix by ROM, temp workaround */
- if (((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_MMC && card_emmc_is_boot_part_en())
+ if (is_soc_rev(CHIP_REV_1_0) && ((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_MMC &&
+ card_emmc_is_boot_part_en())
image_offset = 0;
return image_offset;
diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
index c24bc079ec..87152ca818 100644
--- a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
+++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
@@ -6,6 +6,7 @@
#include <log.h>
#include <asm/io.h>
#include <linux/delay.h>
+#include <asm/arch/sys_proto.h>
#include "upower_soc_defs.h"
#include "upower_api.h"
@@ -191,20 +192,22 @@ int upower_init(void)
if (ret != UPWR_REQ_OK)
printk("Faliure %d\n", ret);
- /* Enable AFBB for AP domain */
- bias.apply = BIAS_APPLY_APD;
- bias.dommode = AFBB_BIAS_MODE;
- ret = upwr_pwm_chng_dom_bias(&bias, NULL);
+ if (is_soc_rev(CHIP_REV_1_0)) {
+ /* Enable AFBB for AP domain */
+ bias.apply = BIAS_APPLY_APD;
+ bias.dommode = AFBB_BIAS_MODE;
+ ret = upwr_pwm_chng_dom_bias(&bias, NULL);
- if (ret)
- printf("Enable AFBB for APD bias fail %d\n", ret);
- else
- printf("Enable AFBB for APD bias ok\n");
+ if (ret)
+ printf("Enable AFBB for APD bias fail %d\n", ret);
+ else
+ printf("Enable AFBB for APD bias ok\n");
- upower_wait_resp();
- ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000);
- if (ret != UPWR_REQ_OK)
- printk("Faliure %d\n", ret);
+ upower_wait_resp();
+ ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000);
+ if (ret != UPWR_REQ_OK)
+ printk("Faliure %d\n", ret);
+ }
return 0;
}
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
new file mode 100644
index 0000000000..c709448411
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -0,0 +1,35 @@
+if ARCH_IMX9
+
+config AHAB_BOOT
+ bool "Support i.MX9 AHAB features"
+ help
+ This option enables the support for AHAB secure boot.
+
+config IMX9
+ bool
+ select ARCH_EARLY_INIT_R
+ select HAS_CAAM
+ select ROM_UNIFIED_SECTIONS
+
+config IMX93
+ bool
+ select IMX9
+ select ARMV8_SPL_EXCEPTION_VECTORS
+
+config SYS_SOC
+ default "imx9"
+
+choice
+ prompt "NXP i.MX9 board select"
+ optional
+
+config TARGET_IMX93_11X11_EVK
+ bool "imx93_11x11_evk"
+ select IMX93
+
+endchoice
+
+source "board/freescale/imx93_evk/Kconfig"
+
+endif
+
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
new file mode 100644
index 0000000000..e1b09ab534
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2022 NXP
+
+obj-y += lowlevel_init.o
+obj-y += soc.o clock.o clock_root.o trdc.o
+
+#ifndef CONFIG_SPL_BUILD
+obj-y += imx_bootaux.o
+#endif
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
new file mode 100644
index 0000000000..7dc33941a9
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -0,0 +1,882 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <errno.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <log.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR;
+
+static struct imx_intpll_rate_table imx9_intpll_tbl[] = {
+ INT_PLL_RATE(1800000000U, 1, 150, 2), /* 1.8Ghz */
+ INT_PLL_RATE(1700000000U, 1, 141, 2), /* 1.7Ghz */
+ INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */
+ INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */
+ INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */
+};
+
+static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
+ FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */
+ FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */
+ FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */
+ FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1),
+ FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1),
+ FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
+ FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
+};
+
+/* return in khz */
+static u32 decode_pll_vco(struct ana_pll_reg *reg, bool fracpll)
+{
+ u32 ctrl;
+ u32 pll_status;
+ u32 div;
+ int rdiv, mfi, mfn, mfd;
+ int clk = 24000;
+
+ ctrl = readl(&reg->ctrl.reg);
+ pll_status = readl(&reg->pll_status);
+ div = readl(&reg->div.reg);
+
+ if (!(ctrl & PLL_CTRL_POWERUP))
+ return 0;
+
+ if (!(pll_status & PLL_STATUS_PLL_LOCK))
+ return 0;
+
+ mfi = (div & GENMASK(24, 16)) >> 16;
+ rdiv = (div & GENMASK(15, 13)) >> 13;
+
+ if (rdiv == 0)
+ rdiv = 1;
+
+ if (fracpll) {
+ mfn = (int)readl(&reg->num.reg);
+ mfn >>= 2;
+ mfd = (int)(readl(&reg->denom.reg) & GENMASK(29, 0));
+
+ clk = clk * (mfi * mfd + mfn) / mfd / rdiv;
+ } else {
+ clk = clk * mfi / rdiv;
+ }
+
+ return (u32)clk;
+}
+
+/* return in khz */
+static u32 decode_pll_out(struct ana_pll_reg *reg, bool fracpll)
+{
+ u32 ctrl = readl(&reg->ctrl.reg);
+ u32 div;
+
+ if (ctrl & PLL_CTRL_CLKMUX_BYPASS)
+ return 24000;
+
+ if (!(ctrl & PLL_CTRL_CLKMUX_EN))
+ return 0;
+
+ div = readl(&reg->div.reg);
+ div &= 0xff; /* odiv */
+
+ if (div == 0)
+ div = 2;
+ else if (div == 1)
+ div = 3;
+
+ return decode_pll_vco(reg, fracpll) / div;
+}
+
+/* return in khz */
+static u32 decode_pll_pfd(struct ana_pll_reg *reg,
+ struct ana_pll_dfs *dfs_reg, bool div2, bool fracpll)
+{
+ u32 pllvco = decode_pll_vco(reg, fracpll);
+ u32 dfs_ctrl = readl(&dfs_reg->dfs_ctrl.reg);
+ u32 dfs_div = readl(&dfs_reg->dfs_div.reg);
+ u32 mfn, mfi;
+ u32 output;
+
+ if (dfs_ctrl & PLL_DFS_CTRL_BYPASS)
+ return pllvco;
+
+ if (!(dfs_ctrl & PLL_DFS_CTRL_ENABLE) ||
+ (div2 && !(dfs_ctrl & PLL_DFS_CTRL_CLKOUT_DIV2)) ||
+ (!div2 && !(dfs_ctrl & PLL_DFS_CTRL_CLKOUT)))
+ return 0;
+
+ mfn = dfs_div & GENMASK(2, 0);
+ mfi = (dfs_div & GENMASK(15, 8)) >> 8;
+
+ if (mfn > 3)
+ return 0; /* valid mfn 0-3 */
+
+ if (mfi == 0 || mfi == 1)
+ return 0; /* valid mfi 2-255 */
+
+ output = (pllvco * 5) / (mfi * 5 + mfn);
+
+ if (div2)
+ return output >> 1;
+
+ return output;
+}
+
+static u32 decode_pll(enum ccm_clk_src pll)
+{
+ switch (pll) {
+ case ARM_PLL_CLK:
+ return decode_pll_out(&ana_regs->arm_pll, false);
+ case SYS_PLL_PG:
+ return decode_pll_out(&ana_regs->sys_pll, false);
+ case SYS_PLL_PFD0:
+ return decode_pll_pfd(&ana_regs->sys_pll,
+ &ana_regs->sys_pll.dfs[0], false, true);
+ case SYS_PLL_PFD0_DIV2:
+ return decode_pll_pfd(&ana_regs->sys_pll,
+ &ana_regs->sys_pll.dfs[0], true, true);
+ case SYS_PLL_PFD1:
+ return decode_pll_pfd(&ana_regs->sys_pll,
+ &ana_regs->sys_pll.dfs[1], false, true);
+ case SYS_PLL_PFD1_DIV2:
+ return decode_pll_pfd(&ana_regs->sys_pll,
+ &ana_regs->sys_pll.dfs[1], true, true);
+ case SYS_PLL_PFD2:
+ return decode_pll_pfd(&ana_regs->sys_pll,
+ &ana_regs->sys_pll.dfs[2], false, true);
+ case SYS_PLL_PFD2_DIV2:
+ return decode_pll_pfd(&ana_regs->sys_pll,
+ &ana_regs->sys_pll.dfs[2], true, true);
+ case AUDIO_PLL_CLK:
+ return decode_pll_out(&ana_regs->audio_pll, true);
+ case DRAM_PLL_CLK:
+ return decode_pll_out(&ana_regs->dram_pll, true);
+ case VIDEO_PLL_CLK:
+ return decode_pll_out(&ana_regs->video_pll, true);
+ default:
+ printf("Invalid clock source to decode\n");
+ break;
+ }
+
+ return 0;
+}
+
+int configure_intpll(enum ccm_clk_src pll, u32 freq)
+{
+ int i;
+ struct imx_intpll_rate_table *rate;
+ struct ana_pll_reg *reg;
+ u32 pll_status;
+
+ for (i = 0; i < ARRAY_SIZE(imx9_intpll_tbl); i++) {
+ if (freq == imx9_intpll_tbl[i].rate)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(imx9_intpll_tbl)) {
+ debug("No matched freq table %u\n", freq);
+ return -EINVAL;
+ }
+
+ rate = &imx9_intpll_tbl[i];
+
+ /* ROM has configured SYS PLL and PFD, no need for it */
+ switch (pll) {
+ case ARM_PLL_CLK:
+ reg = &ana_regs->arm_pll;
+ break;
+ default:
+ return -EPERM;
+ }
+
+ /* Bypass the PLL to ref */
+ writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_set);
+
+ /* disable pll and output */
+ writel(PLL_CTRL_CLKMUX_EN | PLL_CTRL_POWERUP, &reg->ctrl.reg_clr);
+
+ /* Program the ODIV, RDIV, MFI */
+ writel((rate->odiv & GENMASK(7, 0)) |
+ ((rate->rdiv << 13 ) & GENMASK(15, 13)) |
+ ((rate->mfi << 16) & GENMASK(24, 16)), &reg->div.reg);
+
+#ifndef CONFIG_TARGET_IMX93_EMU
+ /* wait 5us */
+ udelay(5);
+#endif
+
+ /* power up the PLL and wait lock (max wait time 100 us) */
+ writel(PLL_CTRL_POWERUP, &reg->ctrl.reg_set);
+
+#ifndef CONFIG_TARGET_IMX93_EMU
+ udelay(100);
+#endif
+
+ pll_status = readl(&reg->pll_status);
+ if (pll_status & PLL_STATUS_PLL_LOCK) {
+ writel(PLL_CTRL_CLKMUX_EN, &reg->ctrl.reg_set);
+
+ /* clear bypass */
+ writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_clr);
+
+ } else {
+ debug("Fail to lock PLL %u\n", pll);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+
+int configure_fracpll(enum ccm_clk_src pll, u32 freq)
+{
+ int i;
+ struct imx_fracpll_rate_table *rate;
+ struct ana_pll_reg *reg;
+ u32 pll_status;
+
+ for (i = 0; i < ARRAY_SIZE(imx9_fracpll_tbl); i++) {
+ if (freq == imx9_fracpll_tbl[i].rate)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(imx9_fracpll_tbl)) {
+ debug("No matched freq table %u\n", freq);
+ return -EINVAL;
+ }
+
+ rate = &imx9_fracpll_tbl[i];
+
+ switch (pll) {
+ case SYS_PLL_PG:
+ reg = &ana_regs->sys_pll;
+ break;
+ case DRAM_PLL_CLK:
+ reg = &ana_regs->dram_pll;
+ break;
+ case VIDEO_PLL_CLK:
+ reg = &ana_regs->video_pll;
+ break;
+ default:
+ return -EPERM;
+ }
+
+ /* Bypass the PLL to ref */
+ writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_set);
+
+ /* disable pll and output */
+ writel(PLL_CTRL_CLKMUX_EN | PLL_CTRL_POWERUP, &reg->ctrl.reg_clr);
+
+ /* Program the ODIV, RDIV, MFI */
+ writel((rate->odiv & GENMASK(7, 0)) |
+ ((rate->rdiv << 13 ) & GENMASK(15, 13)) |
+ ((rate->mfi << 16) & GENMASK(24, 16)), &reg->div.reg);
+
+ /* Set SPREAD_SPECRUM enable to 0 */
+ writel(PLL_SS_EN, &reg->ss.reg_clr);
+
+ /* Program NUMERATOR and DENOMINATOR */
+ writel((rate->mfn << 2), &reg->num.reg);
+ writel((rate->mfd & GENMASK(29, 0)), &reg->denom.reg);
+
+#ifndef CONFIG_TARGET_IMX93_EMU
+ /* wait 5us */
+ udelay(5);
+#endif
+
+ /* power up the PLL and wait lock (max wait time 100 us) */
+ writel(PLL_CTRL_POWERUP, &reg->ctrl.reg_set);
+
+#ifndef CONFIG_TARGET_IMX93_EMU
+ udelay(100);
+#endif
+
+ pll_status = readl(&reg->pll_status);
+ if (pll_status & PLL_STATUS_PLL_LOCK) {
+ writel(PLL_CTRL_CLKMUX_EN, &reg->ctrl.reg_set);
+
+#ifndef CONFIG_TARGET_IMX93_EMU
+ /* check the MFN is updated */
+ pll_status = readl(&reg->pll_status);
+ if ((pll_status & ~0x3) != (rate->mfn << 2)) {
+ debug("MFN update not matched, pll_status 0x%x, mfn 0x%x\n",
+ pll_status, rate->mfn);
+ return -EIO;
+ }
+#endif
+ /* clear bypass */
+ writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_clr);
+
+ } else {
+ debug("Fail to lock PLL %u\n", pll);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+int configure_pll_pfd(enum ccm_clk_src pll_pfg, u32 mfi, u32 mfn, bool div2_en)
+{
+ struct ana_pll_dfs *dfs;
+ struct ana_pll_reg *reg;
+ u32 dfs_status;
+ u32 index;
+
+ if (mfn > 3)
+ return -EINVAL; /* valid mfn 0-3 */
+
+ if (mfi < 2 || mfi > 255)
+ return -EINVAL; /* valid mfi 2-255 */
+
+ switch (pll_pfg) {
+ case SYS_PLL_PFD0:
+ reg = &ana_regs->sys_pll;
+ index = 0;
+ break;
+ case SYS_PLL_PFD1:
+ reg = &ana_regs->sys_pll;
+ index = 1;
+ break;
+ case SYS_PLL_PFD2:
+ reg = &ana_regs->sys_pll;
+ index = 2;
+ break;
+ default:
+ return -EPERM;
+ }
+
+ dfs = &reg->dfs[index];
+
+ /* Bypass the DFS to PLL VCO */
+ writel(PLL_DFS_CTRL_BYPASS, &dfs->dfs_ctrl.reg_set);
+
+ /* disable DFS and output */
+ writel(PLL_DFS_CTRL_ENABLE | PLL_DFS_CTRL_CLKOUT |
+ PLL_DFS_CTRL_CLKOUT_DIV2, &dfs->dfs_ctrl.reg_clr);
+
+ writel(((mfi << 8) & GENMASK(15, 8)) | (mfn & GENMASK(2, 0)),
+ &dfs->dfs_div.reg);
+
+ writel(PLL_DFS_CTRL_CLKOUT, &dfs->dfs_ctrl.reg_set);
+ if (div2_en)
+ writel(PLL_DFS_CTRL_CLKOUT_DIV2, &dfs->dfs_ctrl.reg_set);
+ writel(PLL_DFS_CTRL_ENABLE, &dfs->dfs_ctrl.reg_set);
+
+#ifndef CONFIG_TARGET_IMX93_EMU
+ /*
+ * As HW expert said: after enabling the DFS, clock will start
+ * coming after 6 cycles output clock period.
+ * 5us is much bigger than expected, so it will be safe
+ */
+ udelay(5);
+#endif
+
+ dfs_status = readl(&reg->dfs_status);
+
+ if (!(dfs_status & (1 << index))) {
+ debug("DFS lock failed\n");
+ return -EIO;
+ }
+
+ /* Bypass the DFS to PLL VCO */
+ writel(PLL_DFS_CTRL_BYPASS, &dfs->dfs_ctrl.reg_clr);
+
+ return 0;
+}
+
+int update_fracpll_mfn(enum ccm_clk_src pll, int mfn)
+{
+ struct ana_pll_reg *reg;
+ bool repoll = false;
+ u32 pll_status;
+ int count = 20;
+
+ switch (pll) {
+ case AUDIO_PLL_CLK:
+ reg = &ana_regs->audio_pll;
+ break;
+ case DRAM_PLL_CLK:
+ reg = &ana_regs->dram_pll;
+ break;
+ case VIDEO_PLL_CLK:
+ reg = &ana_regs->video_pll;
+ break;
+ default:
+ printf("Invalid pll %u for update FRAC PLL MFN\n", pll);
+ return -EINVAL;
+ }
+
+ if (readl(&reg->pll_status) & PLL_STATUS_PLL_LOCK)
+ repoll = true;
+
+ mfn <<= 2;
+ writel(mfn, &reg->num);
+
+ if (repoll) {
+ do {
+ pll_status = readl(&reg->pll_status);
+ udelay(5);
+ count--;
+ } while (((pll_status & ~0x3) != (u32)mfn) && count > 0);
+
+ if (count <= 0) {
+ printf("update MFN timeout, pll_status 0x%x, mfn 0x%x\n",
+ pll_status, mfn);
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+
+int update_pll_pfd_mfn(enum ccm_clk_src pll_pfd, u32 mfn)
+{
+ struct ana_pll_dfs *dfs;
+ u32 val;
+ u32 index;
+
+ switch (pll_pfd) {
+ case SYS_PLL_PFD0:
+ case SYS_PLL_PFD0_DIV2:
+ index = 0;
+ break;
+ case SYS_PLL_PFD1:
+ case SYS_PLL_PFD1_DIV2:
+ index = 1;
+ break;
+ case SYS_PLL_PFD2:
+ case SYS_PLL_PFD2_DIV2:
+ index = 2;
+ break;
+ default:
+ printf("Invalid pfd %u for update PLL PFD MFN\n", pll_pfd);
+ return -EINVAL;
+ }
+
+ dfs = &ana_regs->sys_pll.dfs[index];
+
+ val = readl(&dfs->dfs_div.reg);
+ val &= ~0x3;
+ val |= mfn & 0x3;
+ writel(val, &dfs->dfs_div.reg);
+
+ return 0;
+}
+
+/* return in khz */
+u32 get_clk_src_rate(enum ccm_clk_src source)
+{
+ u32 ctrl;
+ bool clk_on;
+
+ switch (source) {
+ case ARM_PLL_CLK:
+ ctrl = readl(&ana_regs->arm_pll.ctrl.reg);
+ case AUDIO_PLL_CLK:
+ ctrl = readl(&ana_regs->audio_pll.ctrl.reg);
+ break;
+ case DRAM_PLL_CLK:
+ ctrl = readl(&ana_regs->dram_pll.ctrl.reg);
+ break;
+ case VIDEO_PLL_CLK:
+ ctrl = readl(&ana_regs->video_pll.ctrl.reg);
+ break;
+ case SYS_PLL_PFD0:
+ case SYS_PLL_PFD0_DIV2:
+ ctrl = readl(&ana_regs->sys_pll.dfs[0].dfs_ctrl.reg);
+ break;
+ case SYS_PLL_PFD1:
+ case SYS_PLL_PFD1_DIV2:
+ ctrl = readl(&ana_regs->sys_pll.dfs[1].dfs_ctrl.reg);
+ break;
+ case SYS_PLL_PFD2:
+ case SYS_PLL_PFD2_DIV2:
+ ctrl = readl(&ana_regs->sys_pll.dfs[2].dfs_ctrl.reg);
+ break;
+ case OSC_24M_CLK:
+ return 24000;
+ default:
+ printf("Invalid clock source to get rate\n");
+ return 0;
+ }
+
+ if (ctrl & PLL_CTRL_HW_CTRL_SEL) {
+ /* When using HW ctrl, check OSCPLL */
+ clk_on = ccm_clk_src_is_clk_on(source);
+ if (clk_on)
+ return decode_pll(source);
+ else
+ return 0;
+ } else {
+ /* controlled by pll registers */
+ return decode_pll(source);
+ }
+}
+
+u32 get_arm_core_clk(void)
+{
+ u32 val;
+ ccm_shared_gpr_get(SHARED_GPR_A55_CLK, &val);
+
+ if (val & SHARED_GPR_A55_CLK_SEL_PLL)
+ return decode_pll(ARM_PLL_CLK) * 1000;
+
+ return ccm_clk_root_get_rate(ARM_A55_CLK_ROOT);
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return get_arm_core_clk();
+ case MXC_IPG_CLK:
+ return ccm_clk_root_get_rate(BUS_WAKEUP_CLK_ROOT);
+ case MXC_CSPI_CLK:
+ return ccm_clk_root_get_rate(LPSPI1_CLK_ROOT);
+ case MXC_ESDHC_CLK:
+ return ccm_clk_root_get_rate(USDHC1_CLK_ROOT);
+ case MXC_ESDHC2_CLK:
+ return ccm_clk_root_get_rate(USDHC2_CLK_ROOT);
+ case MXC_ESDHC3_CLK:
+ return ccm_clk_root_get_rate(USDHC3_CLK_ROOT);
+ case MXC_UART_CLK:
+ return ccm_clk_root_get_rate(LPUART1_CLK_ROOT);
+ case MXC_FLEXSPI_CLK:
+ return ccm_clk_root_get_rate(FLEXSPI1_CLK_ROOT);
+ default:
+ return -1;
+ };
+
+ return -1;
+};
+
+int enable_i2c_clk(unsigned char enable, u32 i2c_num)
+{
+ if (i2c_num > 7)
+ return -EINVAL;
+
+ if (enable) {
+ /* 24M */
+ ccm_lpcg_on(CCGR_I2C1 + i2c_num, false);
+ ccm_clk_root_cfg(LPI2C1_CLK_ROOT + i2c_num, OSC_24M_CLK, 1);
+ ccm_lpcg_on(CCGR_I2C1 + i2c_num, true);
+ } else {
+ ccm_lpcg_on(CCGR_I2C1 + i2c_num, false);
+ }
+
+ return 0;
+}
+
+u32 imx_get_i2cclk(u32 i2c_num)
+{
+ if (i2c_num > 7)
+ return -EINVAL;
+
+ return ccm_clk_root_get_rate(LPI2C1_CLK_ROOT + i2c_num);
+}
+
+u32 get_lpuart_clk(void)
+{
+ return mxc_get_clock(MXC_UART_CLK);
+}
+
+void init_uart_clk(u32 index)
+{
+ switch(index) {
+ case LPUART1_CLK_ROOT:
+ /* 24M */
+ ccm_lpcg_on(CCGR_URT1, false);
+ ccm_clk_root_cfg(LPUART1_CLK_ROOT, OSC_24M_CLK, 1);
+ ccm_lpcg_on(CCGR_URT1, true);
+ break;
+ default:
+ break;
+ }
+}
+
+void init_clk_usdhc(u32 index)
+{
+ /* 400 Mhz */
+ switch (index) {
+ case 0:
+ ccm_lpcg_on(CCGR_USDHC1, 0);
+ ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, 2);
+ ccm_lpcg_on(CCGR_USDHC1, 1);
+ break;
+ case 1:
+ ccm_lpcg_on(CCGR_USDHC2, 0);
+ ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, 2);
+ ccm_lpcg_on(CCGR_USDHC2, 1);
+ break;
+ case 2:
+ ccm_lpcg_on(CCGR_USDHC3, 0);
+ ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, 2);
+ ccm_lpcg_on(CCGR_USDHC3, 1);
+ break;
+ default:
+ return;
+ };
+}
+
+void enable_usboh3_clk(unsigned char enable)
+{
+ if (enable) {
+ ccm_clk_root_cfg(HSIO_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ ccm_lpcg_on(CCGR_USBC, 1);
+ } else {
+ ccm_lpcg_on(CCGR_USBC, 0);
+ }
+}
+
+#ifdef CONFIG_SPL_BUILD
+void dram_pll_init(ulong pll_val)
+{
+ configure_fracpll(DRAM_PLL_CLK, pll_val);
+}
+
+void dram_enable_bypass(ulong clk_val)
+{
+ switch (clk_val) {
+ case MHZ(400):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2);
+ break;
+ case MHZ(333):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD0, 3);
+ break;
+ case MHZ(200):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 4);
+ break;
+ case MHZ(100):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 8);
+ break;
+ default:
+ printf("No matched freq table %lu\n", clk_val);
+ return;
+ }
+
+ /* Set DRAM APB to 133Mhz */
+ ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* Switch from DRAM clock root from PLL to CCM */
+ ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_CCM);
+}
+
+void dram_disable_bypass(void)
+{
+ /* Set DRAM APB to 133Mhz */
+ ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* Switch from DRAM clock root from CCM to PLL */
+ ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL);
+}
+#endif
+
+int clock_init(void)
+{
+ /* Set A55 periphal to 333M */
+ ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3);
+ /* Set A55 mtr bus to 133M */
+ ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+
+ /* Sentinel to 200M */
+ ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2);
+ /* Bus_wakeup to 133M */
+ ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* Bus_AON to 133M */
+ ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* M33 to 200M */
+ ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2);
+ /* WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for generating MII clock at 2.5M */
+ ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2);
+ /* SWO TRACE to 133M */
+ ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* M33 systetick to 133M */
+ ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* NIC to 400M */
+ ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2);
+ /* NIC_APB to 133M */
+ ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+
+ /* allow for non-secure access */
+ int i;
+ for (i = 0; i < OSCPLL_END; i++)
+ ccm_clk_src_tz_access(i, true, false, false);
+
+ for (i = 0; i < CLK_ROOT_NUM; i++)
+ ccm_clk_root_tz_access(i, true, false, false);
+
+ for (i = 0; i < CCGR_NUM; i++)
+ ccm_lpcg_tz_access(i, true, false, false);
+
+ for (i = 0; i < SHARED_GPR_NUM; i++)
+ ccm_shared_gpr_tz_access(i, true, false, false);
+
+ return 0;
+}
+
+int set_clk_eqos(enum enet_freq type)
+{
+ u32 eqos_post_div;
+
+ switch (type) {
+ case ENET_125MHZ:
+ eqos_post_div = 2; /* 250M clock */
+ break;
+ case ENET_50MHZ:
+ eqos_post_div = 5; /* 100M clock */
+ break;
+ case ENET_25MHZ:
+ eqos_post_div = 10; /* 50M clock*/
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* disable the clock first */
+ ccm_lpcg_on(CCGR_ENETQOS, false);
+
+ ccm_clk_root_cfg(ENET_CLK_ROOT, SYS_PLL_PFD0_DIV2, eqos_post_div);
+ ccm_clk_root_cfg(ENET_TIMER2_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5);
+
+ /* enable clock */
+ ccm_lpcg_on(CCGR_ENETQOS, true);
+
+ return 0;
+}
+
+u32 imx_get_eqos_csr_clk(void)
+{
+ return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT);
+}
+
+u32 imx_get_fecclk(void)
+{
+ return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT);
+}
+
+int set_clk_enet(enum enet_freq type)
+{
+ u32 div;
+
+ /* disable the clock first */
+ ccm_lpcg_on(CCGR_ENET1, false);
+
+ switch (type) {
+ case ENET_125MHZ:
+ div = 2; /* 250Mhz */
+ break;
+ case ENET_50MHZ:
+ div = 5; /* 100Mhz */
+ break;
+ case ENET_25MHZ:
+ div = 10; /* 50Mhz */
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ccm_clk_root_cfg(ENET_REF_CLK_ROOT, SYS_PLL_PFD0_DIV2, div);
+ ccm_clk_root_cfg(ENET_TIMER1_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5);
+
+#ifdef CONFIG_FEC_MXC_25M_REF_CLK
+ ccm_clk_root_cfg(ENET_REF_PHY_CLK_ROOT, SYS_PLL_PFD0_DIV2, 20);
+#endif
+
+ /* enable clock */
+ ccm_lpcg_on(CCGR_ENET1, true);
+
+ return 0;
+}
+
+void mxs_set_lcdclk(u32 base_addr, u32 freq)
+{
+ u32 div, i, krate, temp;
+ u32 best = 0, best_div = 0, best_pll = 0;
+
+ debug("%s to set rate to %dkhz\n", __func__, freq);
+
+ for (i = 0; i < ARRAY_SIZE(imx9_fracpll_tbl); i++) {
+ krate = imx9_fracpll_tbl[i].rate / 1000;
+ div = (krate + freq - 1) / freq;
+
+ if (div > 256)
+ continue;
+
+ temp = krate / div;
+ if (best == 0 || temp > best) {
+ best = temp;
+ best_div = div;
+ best_pll = imx9_fracpll_tbl[i].rate;
+ }
+ }
+
+ if (best == 0) {
+ printf("Can't find parent clock for LCDIF, target freq: %u\n", freq);
+ return;
+ }
+
+ /* Select to video PLL */
+ debug("%s, best_pll = %u, div = %u\n", __func__, best_pll, best_div);
+
+ configure_fracpll(VIDEO_PLL_CLK, best_pll);
+ ccm_clk_root_cfg(MEDIA_DISP_PIX_CLK_ROOT, VIDEO_PLL_CLK, best_div);
+}
+
+/*
+ * Dump some clockes.
+ */
+#ifndef CONFIG_SPL_BUILD
+int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 freq;
+
+ freq = decode_pll(ARM_PLL_CLK);
+ printf("ARM_PLL %8d MHz\n", freq / 1000);
+ freq = decode_pll(DRAM_PLL_CLK);
+ printf("DRAM_PLL %8d MHz\n", freq / 1000);
+ freq = decode_pll(SYS_PLL_PFD0);
+ printf("SYS_PLL_PFD0 %8d MHz\n", freq / 1000);
+ freq = decode_pll(SYS_PLL_PFD0_DIV2);
+ printf("SYS_PLL_PFD0_DIV2 %8d MHz\n", freq / 1000);
+ freq = decode_pll(SYS_PLL_PFD1);
+ printf("SYS_PLL_PFD1 %8d MHz\n", freq / 1000);
+ freq = decode_pll(SYS_PLL_PFD1_DIV2);
+ printf("SYS_PLL_PFD1_DIV2 %8d MHz\n", freq / 1000);
+ freq = decode_pll(SYS_PLL_PFD2);
+ printf("SYS_PLL_PFD2 %8d MHz\n", freq / 1000);
+ freq = decode_pll(SYS_PLL_PFD2_DIV2);
+ printf("SYS_PLL_PFD2_DIV2 %8d MHz\n", freq / 1000);
+ freq = mxc_get_clock(MXC_ARM_CLK);
+ printf("ARM CORE %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(MXC_IPG_CLK);
+ printf("IPG %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(MXC_UART_CLK);
+ printf("UART3 %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(MXC_ESDHC_CLK);
+ printf("USDHC1 %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(MXC_FLEXSPI_CLK);
+ printf("FLEXSPI %8d MHz\n", freq / 1000000);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
+ "display clocks",
+ ""
+);
+#endif
+
diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c
new file mode 100644
index 0000000000..5748e28ff0
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/clock_root.c
@@ -0,0 +1,450 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/global_data.h>
+#include <linux/iopoll.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
+
+static enum ccm_clk_src clk_root_mux[][4] = {
+ { OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, SYS_PLL_PFD2 }, /* bus */
+ { OSC_24M_CLK, SYS_PLL_PFD0_DIV2, SYS_PLL_PFD1_DIV2, SYS_PLL_PFD2_DIV2 }, /* non-IO */
+ { OSC_24M_CLK, SYS_PLL_PFD0_DIV2, SYS_PLL_PFD1_DIV2, VIDEO_PLL_CLK }, /* IO*/
+ { OSC_24M_CLK, SYS_PLL_PFD0, AUDIO_PLL_CLK, EXT_CLK }, /* TPM */
+ { OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, EXT_CLK }, /* Audio */
+ { OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, SYS_PLL_PFD0 }, /* Video */
+ { OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, AUDIO_PLL_CLK }, /* CKO1 */
+ { OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, VIDEO_PLL_CLK }, /* CKO2 */
+ { OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, SYS_PLL_PFD2 }, /* CAMSCAN */
+};
+
+static struct clk_root_map clk_root_array[] = {
+ { ARM_A55_PERIPH_CLK_ROOT, 0 },
+ { ARM_A55_MTR_BUS_CLK_ROOT, 2 },
+ { ARM_A55_CLK_ROOT, 0 },
+ { M33_CLK_ROOT, 2 },
+ { SENTINEL_CLK_ROOT, 2 },
+ { BUS_WAKEUP_CLK_ROOT, 2 },
+ { BUS_AON_CLK_ROOT, 2 },
+ { WAKEUP_AXI_CLK_ROOT, 0 },
+ { SWO_TRACE_CLK_ROOT, 2 },
+ { M33_SYSTICK_CLK_ROOT, 2 },
+ { FLEXIO1_CLK_ROOT, 2 },
+ { FLEXIO2_CLK_ROOT, 2 },
+ { LPIT1_CLK_ROOT, 2 },
+ { LPIT2_CLK_ROOT, 2 },
+ { LPTMR1_CLK_ROOT, 2 },
+ { LPTMR2_CLK_ROOT, 2 },
+ { TPM1_CLK_ROOT, 3 },
+ { TPM2_CLK_ROOT, 3 },
+ { TPM3_CLK_ROOT, 3 },
+ { TPM4_CLK_ROOT, 3 },
+ { TPM5_CLK_ROOT, 3 },
+ { TPM6_CLK_ROOT, 3 },
+ { FLEXSPI1_CLK_ROOT, 0 },
+ { CAN1_CLK_ROOT, 2 },
+ { CAN2_CLK_ROOT, 2 },
+ { LPUART1_CLK_ROOT, 2 },
+ { LPUART2_CLK_ROOT, 2 },
+ { LPUART3_CLK_ROOT, 2 },
+ { LPUART4_CLK_ROOT, 2 },
+ { LPUART5_CLK_ROOT, 2 },
+ { LPUART6_CLK_ROOT, 2 },
+ { LPUART7_CLK_ROOT, 2 },
+ { LPUART8_CLK_ROOT, 2 },
+ { LPI2C1_CLK_ROOT, 2 },
+ { LPI2C2_CLK_ROOT, 2 },
+ { LPI2C3_CLK_ROOT, 2 },
+ { LPI2C4_CLK_ROOT, 2 },
+ { LPI2C5_CLK_ROOT, 2 },
+ { LPI2C6_CLK_ROOT, 2 },
+ { LPI2C7_CLK_ROOT, 2 },
+ { LPI2C8_CLK_ROOT, 2 },
+ { LPSPI1_CLK_ROOT, 2 },
+ { LPSPI2_CLK_ROOT, 2 },
+ { LPSPI3_CLK_ROOT, 2 },
+ { LPSPI4_CLK_ROOT, 2 },
+ { LPSPI5_CLK_ROOT, 2 },
+ { LPSPI6_CLK_ROOT, 2 },
+ { LPSPI7_CLK_ROOT, 2 },
+ { LPSPI8_CLK_ROOT, 2 },
+ { I3C1_CLK_ROOT, 2 },
+ { I3C2_CLK_ROOT, 2 },
+ { USDHC1_CLK_ROOT, 0 },
+ { USDHC2_CLK_ROOT, 0 },
+ { USDHC3_CLK_ROOT, 0 },
+ { SAI1_CLK_ROOT, 4 },
+ { SAI2_CLK_ROOT, 4 },
+ { SAI3_CLK_ROOT, 4 },
+ { CCM_CKO1_CLK_ROOT, 6 },
+ { CCM_CKO2_CLK_ROOT, 7 },
+ { CCM_CKO3_CLK_ROOT, 6 },
+ { CCM_CKO4_CLK_ROOT, 7 },
+ { HSIO_CLK_ROOT, 2 },
+ { HSIO_USB_TEST_60M_CLK_ROOT, 2 },
+ { HSIO_ACSCAN_80M_CLK_ROOT, 2 },
+ { HSIO_ACSCAN_480M_CLK_ROOT, 0 },
+ { NIC_CLK_ROOT, 0 },
+ { NIC_APB_CLK_ROOT, 2 },
+ { ML_APB_CLK_ROOT, 2 },
+ { ML_CLK_ROOT, 0 },
+ { MEDIA_AXI_CLK_ROOT, 0 },
+ { MEDIA_APB_CLK_ROOT, 2 },
+ { MEDIA_LDB_CLK_ROOT, 5 },
+ { MEDIA_DISP_PIX_CLK_ROOT, 5 },
+ { CAM_PIX_CLK_ROOT, 5 },
+ { MIPI_TEST_BYTE_CLK_ROOT, 5 },
+ { MIPI_PHY_CFG_CLK_ROOT, 5 },
+ { DRAM_ALT_CLK_ROOT, 0 },
+ { DRAM_APB_CLK_ROOT, 1 },
+ { ADC_CLK_ROOT, 2 },
+ { PDM_CLK_ROOT, 4 },
+ { TSTMR1_CLK_ROOT, 2 },
+ { TSTMR2_CLK_ROOT, 2 },
+ { MQS1_CLK_ROOT, 4 },
+ { MQS2_CLK_ROOT, 4 },
+ { AUDIO_XCVR_CLK_ROOT, 1 },
+ { SPDIF_CLK_ROOT, 4 },
+ { ENET_CLK_ROOT, 1 },
+ { ENET_TIMER1_CLK_ROOT, 2 },
+ { ENET_TIMER2_CLK_ROOT, 2 },
+ { ENET_REF_CLK_ROOT, 1 },
+ { ENET_REF_PHY_CLK_ROOT, 2 },
+ { I3C1_SLOW_CLK_ROOT, 2 },
+ { I3C2_SLOW_CLK_ROOT, 2 },
+ { USB_PHY_BURUNIN_CLK_ROOT, 2 },
+ { PAL_CAME_SCAN_CLK_ROOT, 8 },
+};
+
+int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable)
+{
+ u32 authen;
+
+ if (oscpll >= OSCPLL_END)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
+
+ /* If using cpulpm, need disable it first */
+ if (authen & CCM_AUTHEN_CPULPM_MODE)
+ return -EPERM;
+
+ if (enable)
+ writel(1, &ccm_reg->clk_oscplls[oscpll].direct);
+ else
+ writel(0, &ccm_reg->clk_oscplls[oscpll].direct);
+
+ return 0;
+}
+
+/* auto mode, enable = DIRECT[ON] | STATUS0[IN_USE] */
+int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable)
+{
+ u32 authen;
+
+ if (oscpll >= OSCPLL_END)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
+
+ /* AUTO CTRL and CPULPM are mutual exclusion, need disable CPULPM first */
+ if (authen & CCM_AUTHEN_CPULPM_MODE)
+ return -EPERM;
+
+ if (enable) {
+ writel(authen | CCM_AUTHEN_AUTO_CTRL,
+ &ccm_reg->clk_oscplls[oscpll].authen);
+ } else
+ writel((authen & ~CCM_AUTHEN_AUTO_CTRL),
+ &ccm_reg->clk_oscplls[oscpll].authen);
+
+ return 0;
+}
+
+int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable)
+{
+ u32 authen;
+
+ if (oscpll >= OSCPLL_END)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
+
+ /* AUTO CTRL and CPULPM are mutual exclusion, need disable AUTO CTRL first */
+ if (authen & CCM_AUTHEN_AUTO_CTRL)
+ return -EPERM;
+
+ if (enable)
+ writel(authen | CCM_AUTHEN_CPULPM_MODE,
+ &ccm_reg->clk_oscplls[oscpll].authen);
+ else
+ writel((authen & ~CCM_AUTHEN_CPULPM_MODE),
+ &ccm_reg->clk_oscplls[oscpll].authen);
+
+ return 0;
+}
+
+int ccm_clk_src_config_lpm(enum ccm_clk_src oscpll, u32 domain, u32 lpm_val)
+{
+ u32 lpm, authen;
+
+ if (oscpll >= OSCPLL_END || domain >= 16)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
+ if (!(authen & CCM_AUTHEN_CPULPM_MODE))
+ return -EPERM;
+
+ if (domain > 7) {
+ lpm = readl(&ccm_reg->clk_oscplls[oscpll].lpm1);
+ lpm &= ~(0x3 << ((domain - 8) * 4));
+ lpm |= (lpm_val & 0x3) << ((domain - 8) * 4);
+ writel(lpm, &ccm_reg->clk_oscplls[oscpll].lpm1);
+ } else {
+ lpm = readl(&ccm_reg->clk_oscplls[oscpll].lpm0);
+ lpm &= ~(0x3 << (domain * 4));
+ lpm |= (lpm_val & 0x3) << (domain * 4);
+ writel(lpm, &ccm_reg->clk_oscplls[oscpll].lpm0);
+ }
+
+ return 0;
+}
+
+bool ccm_clk_src_is_clk_on(enum ccm_clk_src oscpll)
+{
+ return !!(readl(&ccm_reg->clk_oscplls[oscpll].status0) & 0x1);
+}
+
+int ccm_clk_src_tz_access(enum ccm_clk_src oscpll,
+ bool non_secure, bool user_mode, bool lock_tz)
+{
+ u32 authen;
+
+ if (oscpll >= OSCPLL_END)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
+
+ authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0;
+ authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0;
+ authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0;
+
+ writel(authen, &ccm_reg->clk_oscplls[oscpll].authen);
+
+ return 0;
+}
+
+int ccm_clk_root_cfg(u32 clk_root_id, enum ccm_clk_src src, u32 div)
+{
+ int i;
+ int ret;
+ u32 mux, status;
+
+ if (clk_root_id >= CLK_ROOT_NUM || div > 256 || div == 0)
+ return -EINVAL;
+
+ mux = clk_root_array[clk_root_id].mux_type;
+
+ for (i = 0; i < 4; i++) {
+ if (src == clk_root_mux[mux][i])
+ break;
+ }
+
+ if (i == 4) {
+ printf("Invalid source [%u] for this clk root\n", src);
+ return -EINVAL;
+ }
+
+ writel((i << 8) | (div - 1), &ccm_reg->clk_roots[clk_root_id].control);
+
+ ret = readl_poll_timeout(&ccm_reg->clk_roots[clk_root_id].status0, status,
+ !(status & CLK_ROOT_STATUS_CHANGING), 200000);
+ if (ret)
+ printf("%s: failed, status: 0x%x\n", __func__,
+ readl(&ccm_reg->clk_roots[clk_root_id].status0));
+
+ return ret;
+};
+
+u32 ccm_clk_root_get_rate(u32 clk_root_id)
+{
+ u32 mux, status, div, rate;
+ enum ccm_clk_src src;
+
+ if (clk_root_id >= CLK_ROOT_NUM)
+ return 0;
+
+ status = readl(&ccm_reg->clk_roots[clk_root_id].control);
+
+ if (status & CLK_ROOT_STATUS_OFF)
+ return 0; /* clock is off */
+
+ mux = (status & CLK_ROOT_MUX_MASK) >> CLK_ROOT_MUX_SHIFT;
+ div = status & CLK_ROOT_DIV_MASK;
+ src = clk_root_mux[clk_root_array[clk_root_id].mux_type][mux];
+
+ rate = get_clk_src_rate(src) * 1000;
+
+ return rate / (div + 1); /* return in hz */
+}
+
+int ccm_clk_root_tz_access(u32 clk_root_id,
+ bool non_secure, bool user_mode, bool lock_tz)
+{
+ u32 authen;
+
+ if (clk_root_id >= CLK_ROOT_NUM)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_roots[clk_root_id].authen);
+
+ authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0;
+ authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0;
+ authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0;
+
+ writel(authen, &ccm_reg->clk_roots[clk_root_id].authen);
+
+ return 0;
+}
+
+int ccm_lpcg_on(u32 lpcg, bool enable)
+{
+ u32 authen;
+
+ if (lpcg >= CCGR_NUM)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen);
+
+ /* If using cpulpm, need disable it first */
+ if (authen & CCM_AUTHEN_CPULPM_MODE)
+ return -EPERM;
+
+ if (enable)
+ writel(1, &ccm_reg->clk_lpcgs[lpcg].direct);
+ else
+ writel(0, &ccm_reg->clk_lpcgs[lpcg].direct);
+
+ return 0;
+
+}
+
+int ccm_lpcg_lpm(u32 lpcg, bool enable)
+{
+ u32 authen;
+
+ if (lpcg >= CCGR_NUM)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen);
+
+ if (enable)
+ writel(authen | CCM_AUTHEN_CPULPM_MODE,
+ &ccm_reg->clk_lpcgs[lpcg].authen);
+ else
+ writel((authen & ~CCM_AUTHEN_CPULPM_MODE),
+ &ccm_reg->clk_lpcgs[lpcg].authen);
+
+ return 0;
+}
+
+int ccm_lpcg_config_lpm(u32 lpcg, u32 domain, u32 lpm_val)
+{
+ u32 lpm, authen;
+
+ if (lpcg >= CCGR_NUM || domain >= 16)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen);
+ if (!(authen & CCM_AUTHEN_CPULPM_MODE))
+ return -EPERM;
+
+ if (domain > 7) {
+ lpm = readl(&ccm_reg->clk_lpcgs[lpcg].lpm1);
+ lpm &= ~(0x3 << ((domain - 8) * 4));
+ lpm |= (lpm_val & 0x3) << ((domain - 8) * 4);
+ writel(lpm, &ccm_reg->clk_lpcgs[lpcg].lpm1);
+ } else {
+ lpm = readl(&ccm_reg->clk_lpcgs[lpcg].lpm0);
+ lpm &= ~(0x3 << (domain * 4));
+ lpm |= (lpm_val & 0x3) << (domain * 4);
+ writel(lpm, &ccm_reg->clk_lpcgs[lpcg].lpm0);
+ }
+
+ return 0;
+}
+
+bool ccm_lpcg_is_clk_on(u32 lpcg)
+{
+ return !!(readl(&ccm_reg->clk_lpcgs[lpcg].status0) & 0x1);
+}
+
+int ccm_lpcg_tz_access(u32 lpcg,
+ bool non_secure, bool user_mode, bool lock_tz)
+{
+ u32 authen;
+
+ if (lpcg >= CCGR_NUM)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen);
+
+ authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0;
+ authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0;
+ authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0;
+
+ writel(authen, &ccm_reg->clk_lpcgs[lpcg].authen);
+
+ return 0;
+}
+
+int ccm_shared_gpr_set(u32 gpr, u32 val)
+{
+ if (gpr >= SHARED_GPR_NUM)
+ return -EINVAL;
+
+ writel(val, &ccm_reg->clk_shared_gpr[gpr].gpr);
+
+ return 0;
+}
+
+int ccm_shared_gpr_get(u32 gpr, u32 *val)
+{
+ if (gpr >= SHARED_GPR_NUM || !val)
+ return -EINVAL;
+
+ *val = readl(&ccm_reg->clk_shared_gpr[gpr].gpr);
+
+ return 0;
+}
+
+
+int ccm_shared_gpr_tz_access(u32 gpr,
+ bool non_secure, bool user_mode, bool lock_tz)
+{
+ u32 authen;
+
+ if (gpr >= SHARED_GPR_NUM)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_shared_gpr[gpr].authen);
+
+ authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0;
+ authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0;
+ authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0;
+
+ writel(authen, &ccm_reg->clk_shared_gpr[gpr].authen);
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c b/arch/arm/mach-imx/imx9/imx_bootaux.c
new file mode 100644
index 0000000000..721e77193e
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/imx_bootaux.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/mach-imx/sys_proto.h>
+#include <command.h>
+#include <elf.h>
+#include <imx_sip.h>
+#include <linux/arm-smccc.h>
+#include <linux/compiler.h>
+#include <cpu_func.h>
+
+int arch_auxiliary_core_check_up(u32 core_id)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0,
+ 0, 0, 0, 0, &res);
+
+ return res.a0;
+}
+
+int arch_auxiliary_core_down(u32 core_id)
+{
+ struct arm_smccc_res res;
+
+ printf("## Stopping auxiliary core\n");
+
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STOP, 0, 0,
+ 0, 0, 0, 0, &res);
+
+ return 0;
+}
+
+int arch_auxiliary_core_up(u32 core_id, ulong addr)
+{
+ struct arm_smccc_res res;
+ u32 stack, pc;
+
+ if (!addr)
+ return -EINVAL;
+
+ stack = *(u32 *)addr;
+ pc = *(u32 *)(addr + 4);
+
+ printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n", stack, pc);
+
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, 0, 0,
+ 0, 0, 0, 0, &res);
+
+ return 0;
+}
+
+/*
+ * To i.MX6SX and i.MX7D, the image supported by bootaux needs
+ * the reset vector at the head for the image, with SP and PC
+ * as the first two words.
+ *
+ * Per the cortex-M reference manual, the reset vector of M4/M7 needs
+ * to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses
+ * of that vector. So to boot M4/M7, the A core must build the M4/M7's reset
+ * vector with getting the PC and SP from image and filling them to
+ * TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself.
+ * The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for
+ * accessing the M4/M7 TCMUL/IDTCM.
+ */
+static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong addr;
+ int ret, up;
+ u32 core = 0;
+ u32 stop = 0;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ if (argc > 2)
+ core = simple_strtoul(argv[2], NULL, 10);
+
+ if (argc > 3)
+ stop = simple_strtoul(argv[3], NULL, 10);
+
+ up = arch_auxiliary_core_check_up(core);
+ if (up) {
+ printf("## Auxiliary core is already up\n");
+ return CMD_RET_SUCCESS;
+ }
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ if (!addr)
+ return CMD_RET_FAILURE;
+
+ ret = arch_auxiliary_core_up(core, addr);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_stopaux(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int ret, up;
+
+ up = arch_auxiliary_core_check_up(0);
+ if (!up) {
+ printf("## Auxiliary core is already down\n");
+ return CMD_RET_SUCCESS;
+ }
+
+ ret = arch_auxiliary_core_down(0);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ stopaux, CONFIG_SYS_MAXARGS, 1, do_stopaux,
+ "Start auxiliary core",
+ "<address> [<core>]\n"
+ " - start auxiliary core [<core>] (default 0),\n"
+ " at address <address>\n"
+);
+
+U_BOOT_CMD(
+ bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
+ "Start auxiliary core",
+ "<address> [<core>]\n"
+ " - start auxiliary core [<core>] (default 0),\n"
+ " at address <address>\n"
+);
diff --git a/arch/arm/mach-imx/imx9/lowlevel_init.S b/arch/arm/mach-imx/imx9/lowlevel_init.S
new file mode 100644
index 0000000000..1dc1dbfcdd
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/lowlevel_init.S
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <config.h>
+
+.align 8
+.global rom_pointer
+rom_pointer:
+ .space 256
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ */
+
+.global save_boot_params
+save_boot_params:
+#ifndef CONFIG_SPL_BUILD
+ /* The firmware provided ATAG/FDT address can be found in r2/x0 */
+ adr x0, rom_pointer
+ stp x1, x2, [x0], #16
+ stp x3, x4, [x0], #16
+#endif
+ /* Returns */
+ b save_boot_params_ret
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
new file mode 100644
index 0000000000..66200dbe3c
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -0,0 +1,614 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <log.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/trdc.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/syscounter.h>
+#include <asm/armv8/mmu.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <env_internal.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <linux/bitops.h>
+#include <asm/setup.h>
+#include <asm/bootm.h>
+#include <asm/arch-imx/cpu.h>
+#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/optee.h>
+#include <linux/delay.h>
+#include <fuse.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rom_api *g_rom_api = (struct rom_api *)0x1980;
+
+enum boot_device get_boot_device(void)
+{
+ volatile gd_t *pgd = gd;
+ int ret;
+ u32 boot;
+ u16 boot_type;
+ u8 boot_instance;
+ enum boot_device boot_dev = SD1_BOOT;
+
+ ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
+ ((uintptr_t)&boot) ^ QUERY_BT_DEV);
+ set_gd(pgd);
+
+ if (ret != ROM_API_OKAY) {
+ puts("ROMAPI: failure at query_boot_info\n");
+ return -1;
+ }
+
+ boot_type = boot >> 16;
+ boot_instance = (boot >> 8) & 0xff;
+
+ switch (boot_type) {
+ case BT_DEV_TYPE_SD:
+ boot_dev = boot_instance + SD1_BOOT;
+ break;
+ case BT_DEV_TYPE_MMC:
+ boot_dev = boot_instance + MMC1_BOOT;
+ break;
+ case BT_DEV_TYPE_NAND:
+ boot_dev = NAND_BOOT;
+ break;
+ case BT_DEV_TYPE_FLEXSPINOR:
+ boot_dev = QSPI_BOOT;
+ break;
+ case BT_DEV_TYPE_USB:
+ boot_dev = boot_instance + USB_BOOT;
+ break;
+ default:
+ break;
+ }
+
+ debug("boot dev %d\n", boot_dev);
+
+ return boot_dev;
+}
+
+bool is_usb_boot(void)
+{
+ enum boot_device bt_dev = get_boot_device();
+ return (bt_dev == USB_BOOT || bt_dev == USB2_BOOT);
+}
+
+void disconnect_from_pc(void)
+{
+ enum boot_device bt_dev = get_boot_device();
+
+ if (bt_dev == USB_BOOT)
+ writel(0x0, USB1_BASE_ADDR + 0x140);
+ else if (bt_dev == USB2_BOOT)
+ writel(0x0, USB2_BASE_ADDR + 0x140);
+
+ return;
+}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+__weak int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int mmc_get_env_dev(void)
+{
+ volatile gd_t *pgd = gd;
+ int ret;
+ u32 boot;
+ u16 boot_type;
+ u8 boot_instance;
+
+ ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
+ ((uintptr_t)&boot) ^ QUERY_BT_DEV);
+ set_gd(pgd);
+
+ if (ret != ROM_API_OKAY) {
+ puts("ROMAPI: failure at query_boot_info\n");
+ return CONFIG_SYS_MMC_ENV_DEV;
+ }
+
+ boot_type = boot >> 16;
+ boot_instance = (boot >> 8) & 0xff;
+
+ debug("boot_type %d, instance %d\n", boot_type, boot_instance);
+
+ /* If not boot from sd/mmc, use default value */
+ if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
+ return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
+
+ return board_mmc_get_env_dev(boot_instance);
+
+}
+#endif
+
+#ifdef CONFIG_USB_PORT_AUTO
+int board_usb_gadget_port_auto(void)
+{
+ enum boot_device bt_dev = get_boot_device();
+ int usb_boot_index = 0;
+
+ if (bt_dev == USB2_BOOT)
+ usb_boot_index = 1;
+
+ printf("auto usb %d\n", usb_boot_index);
+
+ return usb_boot_index;
+}
+#endif
+
+static void set_cpu_info(struct sentinel_get_info_data *info)
+{
+ gd->arch.soc_rev = info->soc;
+ gd->arch.lifecycle = info->lc;
+ memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32));
+}
+
+u32 get_cpu_rev(void)
+{
+ u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
+ return (MXC_CPU_IMX93 << 12) | (CHIP_REV_1_0 + rev);
+}
+
+#define UNLOCK_WORD 0xD928C520 /* unlock word */
+#define REFRESH_WORD 0xB480A602 /* refresh word */
+
+static void disable_wdog(void __iomem *wdog_base)
+{
+ u32 val_cs = readl(wdog_base + 0x00);
+
+ if (!(val_cs & 0x80))
+ return;
+
+ /* default is 32bits cmd */
+ writel(REFRESH_WORD, (wdog_base + 0x04)); /* Refresh the CNT */
+
+ if (!(val_cs & 0x800)) {
+ writel(UNLOCK_WORD, (wdog_base + 0x04));
+ while (!(readl(wdog_base + 0x00) & 0x800))
+ ;
+ }
+ writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
+ writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
+ writel(0x2120, (wdog_base + 0x00)); /* Disable it and set update */
+
+ while (!(readl(wdog_base + 0x00) & 0x400))
+ ;
+}
+
+void init_wdog(void)
+{
+ u32 src_val;
+
+ disable_wdog((void __iomem *)WDG3_BASE_ADDR);
+ disable_wdog((void __iomem *)WDG4_BASE_ADDR);
+ disable_wdog((void __iomem *)WDG5_BASE_ADDR);
+
+ src_val = readl(0x54460018); /* reset mask */
+ src_val &= ~0x1c;
+ writel(src_val, 0x54460018);
+}
+
+static struct mm_region imx93_mem_map[] = {
+ {
+ /* ROM */
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x100000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+ /* TCM */
+ .virt = 0x201c0000UL,
+ .phys = 0x201c0000UL,
+ .size = 0x80000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* OCRAM */
+ .virt = 0x20480000UL,
+ .phys = 0x20480000UL,
+ .size = 0xA0000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+ /* AIPS */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* Flexible Serial Peripheral Interface */
+ .virt = 0x28000000UL,
+ .phys = 0x28000000UL,
+ .size = 0x30000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* DRAM1 */
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = PHYS_SDRAM_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+ /* empty entrie to split table entry 5 if needed when TEEs are used */
+ 0,
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = imx93_mem_map;
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ u32 val[2] = {};
+ int ret;
+
+ if (dev_id == 0) {
+ ret = fuse_read(39, 3, &val[0]);
+ if (ret)
+ goto err;
+
+ ret = fuse_read(39, 4, &val[1]);
+ if (ret)
+ goto err;
+
+ mac[0] = val[1] >> 8;
+ mac[1] = val[1];
+ mac[2] = val[0] >> 24;
+ mac[3] = val[0] >> 16;
+ mac[4] = val[0] >> 8;
+ mac[5] = val[0];
+
+ } else {
+ ret = fuse_read(39, 5, &val[0]);
+ if (ret)
+ goto err;
+
+ ret = fuse_read(39, 4, &val[1]);
+ if (ret)
+ goto err;
+
+ mac[0] = val[1] >> 24;
+ mac[1] = val[1] >> 16;
+ mac[2] = val[0] >> 24;
+ mac[3] = val[0] >> 16;
+ mac[4] = val[0] >> 8;
+ mac[5] = val[0];
+ }
+
+ debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
+ __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ return;
+err:
+ memset(mac, 0, 6);
+ printf("%s: fuse read err: %d\n", __func__, ret);
+}
+
+int print_cpuinfo(void)
+{
+ u32 cpurev;
+
+ cpurev = get_cpu_rev();
+
+ printf("CPU: i.MX93 rev%d.%d at %d MHz\n",
+ (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+
+ return 0;
+}
+
+int arch_misc_init(void)
+{
+ return 0;
+}
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+ return ft_add_optee_node(blob, bd);
+}
+
+#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ printf("UID: 0x%x 0x%x 0x%x 0x%x\n",
+ gd->arch.uid[0], gd->arch.uid[1], gd->arch.uid[2], gd->arch.uid[3]);
+
+ serialnr->low = gd->arch.uid[0];
+ serialnr->high = gd->arch.uid[3];
+}
+#endif
+
+int arch_cpu_init(void)
+{
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ /* Disable wdog */
+ init_wdog();
+
+ clock_init();
+
+ trdc_early_init();
+ }
+
+ return 0;
+}
+
+int arch_cpu_init_dm(void)
+{
+ struct udevice *devp;
+ int node, ret;
+ u32 res;
+ struct sentinel_get_info_data info;
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4");
+
+ ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
+ if (ret)
+ return ret;
+
+ ret = ahab_get_info(&info, &res);
+ if (ret)
+ return ret;
+
+ set_cpu_info(&info);
+
+ return 0;
+}
+
+#ifdef CONFIG_ARCH_EARLY_INIT_R
+int arch_early_init_r(void)
+{
+ struct udevice *devp;
+ int node, ret;
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4");
+
+ ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
+ if (ret) {
+ printf("could not get S400 mu %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+int timer_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
+ unsigned long freq = readl(&sctr->cntfid0);
+
+ /* Update with accurate clock frequency */
+ asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
+
+ clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
+ SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
+#endif
+
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ return 0;
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ enum boot_device dev = get_boot_device();
+ enum env_location env_loc = ENVL_UNKNOWN;
+
+ if (prio)
+ return env_loc;
+
+ switch (dev) {
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+ case QSPI_BOOT:
+ env_loc = ENVL_SPI_FLASH;
+ break;
+#endif
+#ifdef CONFIG_ENV_IS_IN_MMC
+ case SD1_BOOT:
+ case SD2_BOOT:
+ case SD3_BOOT:
+ case MMC1_BOOT:
+ case MMC2_BOOT:
+ case MMC3_BOOT:
+ env_loc = ENVL_MMC;
+ break;
+#endif
+ default:
+#if defined(CONFIG_ENV_IS_NOWHERE)
+ env_loc = ENVL_NOWHERE;
+#endif
+ break;
+ }
+
+ return env_loc;
+}
+
+int mix_power_init(enum mix_power_domain pd)
+{
+ enum src_mix_slice_id mix_id;
+ enum src_mem_slice_id mem_id;
+ struct src_mix_slice_regs *mix_regs;
+ struct src_mem_slice_regs *mem_regs;
+ struct src_general_regs *global_regs;
+ u32 scr, val;
+
+ switch (pd) {
+ case MIX_PD_MEDIAMIX:
+ mix_id = SRC_MIX_MEDIA;
+ mem_id = SRC_MEM_MEDIA;
+ scr = BIT(5);
+
+ /* Enable S400 handshake */
+ struct blk_ctrl_s_aonmix_regs *s_regs =
+ (struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
+
+ setbits_le32(&s_regs->lp_handshake[0], BIT(13));
+ break;
+ case MIX_PD_MLMIX:
+ mix_id = SRC_MIX_ML;
+ mem_id = SRC_MEM_ML;
+ scr = BIT(4);
+ break;
+ case MIX_PD_DDRMIX:
+ mix_id = SRC_MIX_DDRMIX;
+ mem_id = SRC_MEM_DDRMIX;
+ scr = BIT(6);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ mix_regs = (struct src_mix_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x400 * (mix_id + 1));
+ mem_regs = (struct src_mem_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x3800 + 0x400 * mem_id);
+ global_regs = (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
+
+ /* Allow NS to set it */
+ setbits_le32(&mix_regs->authen_ctrl, BIT(9));
+
+ clrsetbits_le32(&mix_regs->psw_ack_ctrl[0], BIT(28), BIT(29));
+
+ /* mix reset will be held until boot core write this bit to 1 */
+ setbits_le32(&global_regs->scr, scr);
+
+ /* Enable mem in Low power auto sequence */
+ setbits_le32(&mem_regs->mem_ctrl, BIT(2));
+
+ /* Set the power down state */
+ val = readl(&mix_regs->func_stat);
+ if (val & SRC_MIX_SLICE_FUNC_STAT_PSW_STAT) {
+ /* The mix is default power off, power down it to make PDN_SFT bit
+ * aligned with FUNC STAT
+ */
+ setbits_le32(&mix_regs->slice_sw_ctrl, BIT(31));
+ val = readl(&mix_regs->func_stat);
+
+ /* Since PSW_STAT is 1, can't be used for power off status (SW_CTRL BIT31 set)) */
+ /* Check the MEM STAT change to ensure SSAR is completed */
+ while (!(val & SRC_MIX_SLICE_FUNC_STAT_MEM_STAT)) {
+ val = readl(&mix_regs->func_stat);
+ }
+
+ /* wait few ipg clock cycles to ensure FSM done and power off status is correct */
+ /* About 5 cycles at 24Mhz, 1us is enough */
+ udelay(1);
+ } else {
+ /* The mix is default power on, Do mix power cycle */
+ setbits_le32(&mix_regs->slice_sw_ctrl, BIT(31));
+ val = readl(&mix_regs->func_stat);
+ while (!(val & SRC_MIX_SLICE_FUNC_STAT_PSW_STAT)) {
+ val = readl(&mix_regs->func_stat);
+ }
+ }
+
+ /* power on */
+ clrbits_le32(&mix_regs->slice_sw_ctrl, BIT(31));
+ val = readl(&mix_regs->func_stat);
+ while (val & SRC_MIX_SLICE_FUNC_STAT_ISO_STAT) {
+ val = readl(&mix_regs->func_stat);
+ }
+
+ return 0;
+}
+
+void disable_isolation(void)
+{
+ struct src_general_regs *global_regs = (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
+ /* clear isolation for usbphy, dsi, csi*/
+ writel(0x0, &global_regs->sp_iso_ctrl);
+}
+
+void soc_power_init(void)
+{
+ mix_power_init(MIX_PD_MEDIAMIX);
+ mix_power_init(MIX_PD_MLMIX);
+
+ disable_isolation();
+}
+
+bool m33_is_rom_kicked(void)
+{
+ struct blk_ctrl_s_aonmix_regs *s_regs =
+ (struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
+
+ if (!(readl(&s_regs->m33_cfg) & BCTRL_S_ANOMIX_M33_CPU_WAIT_MASK))
+ return true;
+
+ return false;
+}
+
+int m33_prepare(void)
+{
+ struct src_mix_slice_regs *mix_regs =
+ (struct src_mix_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x400 * (SRC_MIX_CM33 + 1));
+ struct src_general_regs *global_regs =
+ (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
+ struct blk_ctrl_s_aonmix_regs *s_regs =
+ (struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
+ u32 val;
+
+ /* Allow NS to set it */
+ setbits_le32(&mix_regs->authen_ctrl, BIT(9));
+
+ if (m33_is_rom_kicked())
+ return -EPERM;
+
+ /* Release reset of M33 */
+ setbits_le32(&global_regs->scr, BIT(0));
+
+ /* Check the reset released in M33 MIX func stat */
+ val = readl(&mix_regs->func_stat);
+ while (!(val & SRC_MIX_SLICE_FUNC_STAT_RST_STAT)) {
+ val = readl(&mix_regs->func_stat);
+ }
+
+ /* Because CPUWAIT is default set, so M33 won't run, Clear it when kick M33 */
+ /* Release Sentinel TROUT */
+ ahab_release_m33_trout();
+
+ /* Mask WDOG1 IRQ from A55, we use it for M33 reset */
+ setbits_le32(&s_regs->ca55_irq_mask[1], BIT(6));
+
+ /* Turn on WDOG1 clock */
+ ccm_lpcg_on(CCGR_WDG1, 1);
+
+ /* Set sentinel LP handshake for M33 reset */
+ setbits_le32(&s_regs->lp_handshake[0], BIT(6));
+
+ /* Clear M33 TCM for ECC */
+ memset((void *)(ulong)0x201e0000, 0, 0x40000);
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
new file mode 100644
index 0000000000..bb137a7912
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -0,0 +1,593 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <div64.h>
+#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/mu_hal.h>
+
+#define DID_NUM 16
+#define MBC_MAX_NUM 4
+#define MRC_MAX_NUM 2
+#define MBC_NUM(HWCFG) ((HWCFG >> 16) & 0xF)
+#define MRC_NUM(HWCFG) ((HWCFG >> 24) & 0x1F)
+
+struct mbc_mem_dom {
+ u32 mem_glbcfg[4];
+ u32 nse_blk_index;
+ u32 nse_blk_set;
+ u32 nse_blk_clr;
+ u32 nsr_blk_clr_all;
+ u32 memn_glbac[8];
+ /* The upper only existed in the beginning of each MBC */
+ u32 mem0_blk_cfg_w[64];
+ u32 mem0_blk_nse_w[16];
+ u32 mem1_blk_cfg_w[8];
+ u32 mem1_blk_nse_w[2];
+ u32 mem2_blk_cfg_w[8];
+ u32 mem2_blk_nse_w[2];
+ u32 mem3_blk_cfg_w[8];
+ u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */
+ u32 reserved[2];
+};
+
+struct mrc_rgn_dom {
+ u32 mrc_glbcfg[4];
+ u32 nse_rgn_indirect;
+ u32 nse_rgn_set;
+ u32 nse_rgn_clr;
+ u32 nse_rgn_clr_all;
+ u32 memn_glbac[8];
+ /* The upper only existed in the beginning of each MRC */
+ u32 rgn_desc_words[16][2]; /* 16 regions at max, 2 words per region */
+ u32 rgn_nse;
+ u32 reserved2[15];
+};
+
+struct mda_inst {
+ u32 mda_w[8];
+};
+
+struct trdc_mgr {
+ u32 trdc_cr;
+ u32 res0[59];
+ u32 trdc_hwcfg0;
+ u32 trdc_hwcfg1;
+ u32 res1[450];
+ struct mda_inst mda[8];
+ u32 res2[15808];
+};
+
+struct trdc_mbc {
+ struct mbc_mem_dom mem_dom[DID_NUM];
+};
+
+struct trdc_mrc {
+ struct mrc_rgn_dom mrc_dom[DID_NUM];
+};
+
+
+int trdc_mda_set_cpu(ulong trdc_reg, u32 mda_inst, u32 mda_reg, u8 sa, u8 dids, u8 did, u8 pe, u8 pidm, u8 pid)
+{
+ struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+ u32 *mda_w = &trdc_base->mda[mda_inst].mda_w[mda_reg];
+ u32 val = readl(mda_w);
+
+ if (val & BIT(29)) /* non-cpu */
+ return -EINVAL;
+
+ val = BIT(31) | ((pid & 0x3f) << 16) | ((pidm & 0x3f) << 8) | ((pe & 0x3) << 6) | ((sa & 0x3) << 14) | ((dids & 0x3) << 4) | (did & 0xf);
+
+ writel(val, mda_w);
+
+ return 0;
+}
+
+int trdc_mda_set_noncpu(ulong trdc_reg, u32 mda_inst, u32 mda_reg, bool did_bypass, u8 sa, u8 pa, u8 did)
+{
+ struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+ u32 *mda_w = &trdc_base->mda[mda_inst].mda_w[mda_reg];
+ u32 val = readl(mda_w);
+
+ if (!(val & BIT(29))) /* cpu */
+ return -EINVAL;
+
+ val = BIT(31) | ((sa & 0x3) << 6) | ((pa & 0x3) << 4) | (did & 0xf);
+ if (did_bypass)
+ val |= BIT(8);
+
+ writel(val, mda_w);
+
+ return 0;
+}
+
+static ulong trdc_get_mbc_base(ulong trdc_reg, u32 mbc_x)
+{
+ struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+ u32 mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0);
+
+ if (mbc_x >= mbc_num)
+ return 0;
+
+ return trdc_reg + 0x10000 + 0x2000 * mbc_x;
+}
+
+static ulong trdc_get_mrc_base(ulong trdc_reg, u32 mrc_x)
+{
+ struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+ u32 mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0);
+ u32 mrc_num = MRC_NUM(trdc_base->trdc_hwcfg0);
+
+ if (mrc_x >= mrc_num)
+ return 0;
+
+ return trdc_reg + 0x10000 + 0x2000 * mbc_num + 0x1000 * mrc_x;
+}
+
+int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, u32 glbac_id, u32 glbac_val)
+{
+ struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
+ struct mbc_mem_dom *mbc_dom;
+
+ if (mbc_base == 0 || glbac_id >= 8)
+ return -EINVAL;
+
+ /* only first dom has the glbac */
+ mbc_dom = &mbc_base->mem_dom[0];
+
+ debug("mbc 0x%lx\n", (ulong)mbc_dom);
+
+ writel(glbac_val, &mbc_dom->memn_glbac[glbac_id]);
+
+ return 0;
+}
+
+int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access, u32 glbac_id)
+{
+ struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
+ struct mbc_mem_dom *mbc_dom;
+ u32 *cfg_w, *nse_w;
+ u32 index, offset, val;
+
+ if (mbc_base == 0 || glbac_id >= 8)
+ return -EINVAL;
+
+ mbc_dom = &mbc_base->mem_dom[dom_x];
+
+ debug("mbc 0x%lx\n", (ulong)mbc_dom);
+
+ switch (mem_x) {
+ case 0:
+ cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8];
+ nse_w = &mbc_dom->mem0_blk_nse_w[blk_x / 32];
+ break;
+ case 1:
+ cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8];
+ nse_w = &mbc_dom->mem1_blk_nse_w[blk_x / 32];
+ break;
+ case 2:
+ cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8];
+ nse_w = &mbc_dom->mem2_blk_nse_w[blk_x / 32];
+ break;
+ case 3:
+ cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8];
+ nse_w = &mbc_dom->mem3_blk_nse_w[blk_x / 32];
+ break;
+ default:
+ return -EINVAL;
+ };
+
+ index = blk_x % 8;
+ offset = index * 4;
+
+ val = readl((void __iomem *)cfg_w);
+
+ val &= ~(0xFU << offset);
+
+ /* MBC0-3
+ * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+ * So select MBC0_MEMN_GLBAC0
+ */
+ if (sec_access) {
+ val |= ((0x0 | (glbac_id & 0x7)) << offset);
+ writel(val, (void __iomem *)cfg_w);
+ } else {
+ val |= ((0x8 | (glbac_id & 0x7)) << offset); /* nse bit set */
+ writel(val, (void __iomem *)cfg_w);
+ }
+
+ return 0;
+}
+
+int trdc_mrc_set_control(ulong trdc_reg, u32 mrc_x, u32 glbac_id, u32 glbac_val)
+{
+ struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x);
+ struct mrc_rgn_dom *mrc_dom;
+
+ if (mrc_base == 0 || glbac_id >= 8)
+ return -EINVAL;
+
+ /* only first dom has the glbac */
+ mrc_dom = &mrc_base->mrc_dom[0];
+
+ debug("mrc_dom 0x%lx\n", (ulong)mrc_dom);
+
+ writel(glbac_val, &mrc_dom->memn_glbac[glbac_id]);
+
+ return 0;
+}
+
+int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, u32 dom_x, u32 addr_start, u32 addr_end, bool sec_access, u32 glbac_id)
+{
+ struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x);
+ struct mrc_rgn_dom *mrc_dom;
+ u32 *desc_w;
+ u32 start, end;
+ u32 i, free = 8;;
+ bool vld, hit = false;
+
+ if (mrc_base == 0 || glbac_id >= 8)
+ return -EINVAL;
+
+ mrc_dom = &mrc_base->mrc_dom[dom_x];
+
+ addr_start &= ~0x3fff;
+ addr_end &= ~0x3fff;
+
+ debug("mrc_dom 0x%lx\n", (ulong)mrc_dom);
+
+ for (i = 0; i < 8; i++) {
+ desc_w = &mrc_dom->rgn_desc_words[i][0];
+
+ debug("desc_w 0x%lx\n", (ulong)desc_w);
+
+ start = readl((void __iomem *)desc_w) & (~0x3fff);
+ end = readl((void __iomem *)(desc_w + 1));
+ vld = end & 0x1;
+ end = end & (~0x3fff);
+
+ if (start == 0 && end == 0 && !vld && free >= 8)
+ free = i;
+
+ /* Check all the region descriptors, even overlap */
+ if (addr_start >= end || addr_end <= start || !vld)
+ continue;
+
+ /* MRC0,1
+ * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+ * So select MRCx_MEMN_GLBAC0
+ */
+ if (sec_access) {
+ writel(start | (glbac_id & 0x7), (void __iomem *)desc_w);
+ writel(end | 0x1, (void __iomem *)(desc_w + 1));
+ } else {
+ writel(start | (glbac_id & 0x7), (void __iomem *)desc_w);
+ writel(end | 0x1 | 0x10, (void __iomem *)(desc_w + 1));
+ }
+
+ if (addr_start >= start && addr_end <= end)
+ hit = true;
+ }
+
+ if (!hit) {
+ if (free >= 8)
+ return -EFAULT;
+
+ desc_w = &mrc_dom->rgn_desc_words[free][0];
+
+ debug("free desc_w 0x%lx\n", (ulong)desc_w);
+ debug("[0x%x] [0x%x]\n", addr_start | (glbac_id & 0x7), addr_end | 0x1);
+
+ if (sec_access) {
+ writel(addr_start | (glbac_id & 0x7), (void __iomem *)desc_w);
+ writel(addr_end | 0x1, (void __iomem *)(desc_w + 1));
+ } else {
+ writel(addr_start | (glbac_id & 0x7), (void __iomem *)desc_w);
+ writel((addr_end | 0x1 | 0x10), (void __iomem *)(desc_w + 1));
+ }
+ }
+
+ return 0;
+}
+
+bool trdc_mrc_enabled(ulong trdc_base)
+{
+ return (!!(readl((void __iomem *)trdc_base) & 0x8000));
+}
+
+bool trdc_mbc_enabled(ulong trdc_base)
+{
+ return (!!(readl((void __iomem *)trdc_base) & 0x4000));
+}
+
+int release_rdc(u8 xrdc)
+{
+ ulong s_mu_base = 0x47520000UL;
+ struct sentinel_msg msg;
+ int ret;
+ u32 rdc_id;
+
+ switch (xrdc) {
+ case 0:
+ rdc_id = 0x74;
+ break;
+ case 1:
+ rdc_id = 0x78;
+ break;
+ case 2:
+ rdc_id = 0x82;
+ break;
+ case 3:
+ rdc_id = 0x86;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 2;
+ msg.command = ELE_RELEASE_RDC_REQ;
+ msg.data[0] = (rdc_id << 8) | 0x2; /* A55 */
+
+ mu_hal_init(s_mu_base);
+ mu_hal_sendmsg(s_mu_base, 0, *((u32 *)&msg));
+ mu_hal_sendmsg(s_mu_base, 1, msg.data[0]);
+
+ ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *)&msg);
+ if (!ret) {
+ ret = mu_hal_receivemsg(s_mu_base, 1, &msg.data[0]);
+ if (!ret) {
+ if ((msg.data[0] & 0xff) == 0xd6)
+ return 0;
+ }
+
+ return -EIO;
+ }
+
+ return ret;
+}
+
+void trdc_early_init(void)
+{
+ int ret = 0, i;
+ ret |= release_rdc(0);
+ ret |= release_rdc(2);
+ ret |= release_rdc(1);
+ ret |= release_rdc(3);
+
+ if (!ret) {
+ /* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX only */
+ trdc_mbc_set_control(0x49010000, 3, 0, 0x7700);
+
+ for (i = 0; i < 40; i++) {
+ trdc_mbc_blk_config(0x49010000, 3, 3, 0, i, true, 0);
+ }
+
+ for (i = 0; i < 40; i++) {
+ trdc_mbc_blk_config(0x49010000, 3, 3, 1, i, true, 0);
+ }
+
+ for (i = 0; i < 40; i++) {
+ trdc_mbc_blk_config(0x49010000, 3, 0, 0, i, true, 0);
+ }
+
+ for (i = 0; i < 40; i++) {
+ trdc_mbc_blk_config(0x49010000, 3, 0, 1, i, true, 0);
+ }
+ }
+}
+
+void trdc_init(void)
+{
+ /* TRDC mega */
+ if (trdc_mrc_enabled(0x49010000)) {
+
+ /* DDR */
+ trdc_mrc_set_control(0x49010000, 0, 0, 0x7777);
+
+ /* S400*/
+ trdc_mrc_region_config(0x49010000, 0, 0, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /* MTR */
+ trdc_mrc_region_config(0x49010000, 0, 1, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /* M33 */
+ trdc_mrc_region_config(0x49010000, 0, 2, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /* A55*/
+ trdc_mrc_region_config(0x49010000, 0, 3, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /* For USDHC1 to DDR, USDHC1 is default force to non-secure */
+ trdc_mrc_region_config(0x49010000, 0, 5, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /* For USDHC2 to DDR, USDHC2 is default force to non-secure */
+ trdc_mrc_region_config(0x49010000, 0, 6, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /* eDMA */
+ trdc_mrc_region_config(0x49010000, 0, 7, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /*CoreSight, TestPort*/
+ trdc_mrc_region_config(0x49010000, 0, 8, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /* DAP */
+ trdc_mrc_region_config(0x49010000, 0, 9, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /*SoC masters */
+ trdc_mrc_region_config(0x49010000, 0, 10, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /*USB*/
+ trdc_mrc_region_config(0x49010000, 0, 11, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ }
+}
+
+#if DEBUG
+int trdc_mbc_control_dump(ulong trdc_reg, u32 mbc_x, u32 glbac_id)
+{
+ struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
+ struct mbc_mem_dom *mbc_dom;
+
+ if (mbc_base == 0 || glbac_id >= 8)
+ return -EINVAL;
+
+ /* only first dom has the glbac */
+ mbc_dom = &mbc_base->mem_dom[0];
+
+ printf("mbc_dom %u glbac %u: 0x%x\n", mbc_x, glbac_id, readl(&mbc_dom->memn_glbac[glbac_id]));
+
+ return 0;
+}
+
+int trdc_mbc_mem_dump(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x, u32 word)
+{
+ struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
+ struct mbc_mem_dom *mbc_dom;
+ u32 *cfg_w;
+
+ if (mbc_base == 0)
+ return -EINVAL;
+
+ mbc_dom = &mbc_base->mem_dom[dom_x];
+
+ switch (mem_x) {
+ case 0:
+ cfg_w = &mbc_dom->mem0_blk_cfg_w[word];
+ break;
+ case 1:
+ cfg_w = &mbc_dom->mem1_blk_cfg_w[word];
+ break;
+ case 2:
+ cfg_w = &mbc_dom->mem2_blk_cfg_w[word];
+ break;
+ case 3:
+ cfg_w = &mbc_dom->mem3_blk_cfg_w[word];
+ break;
+ default:
+ return -EINVAL;
+ };
+
+ printf("mbc_dom %u dom %u mem %u word %u: 0x%x\n", mbc_x, dom_x, mem_x, word, readl((void __iomem *)cfg_w));
+
+ return 0;
+}
+
+int trdc_mrc_control_dump(ulong trdc_reg, u32 mrc_x, u32 glbac_id)
+{
+ struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x);
+ struct mrc_rgn_dom *mrc_dom;
+
+ if (mrc_base == 0 || glbac_id >= 8)
+ return -EINVAL;
+
+ /* only first dom has the glbac */
+ mrc_dom = &mrc_base->mrc_dom[0];
+
+ printf("mrc_dom %u glbac %u: 0x%x\n", mrc_x, glbac_id, readl(&mrc_dom->memn_glbac[glbac_id]));
+
+ return 0;
+}
+
+void trdc_dump(void)
+{
+ u32 i;
+ printf("TRDC AONMIX MBC\n");
+
+ trdc_mbc_control_dump(0x44270000, 0, 0);
+ trdc_mbc_control_dump(0x44270000, 1, 0);
+
+ for (i = 0; i < 11; i++) {
+ trdc_mbc_mem_dump(0x44270000, 0, 3, 0, i);
+ }
+ for (i = 0; i < 1; i++) {
+ trdc_mbc_mem_dump(0x44270000, 0, 3, 1, i);
+ }
+
+ for (i = 0; i < 4; i++) {
+ trdc_mbc_mem_dump(0x44270000, 1, 3, 0, i);
+ }
+ for (i = 0; i < 4; i++) {
+ trdc_mbc_mem_dump(0x44270000, 1, 3, 1, i);
+ }
+
+ printf("TRDC WAKEUP MBC\n");
+
+ trdc_mbc_control_dump(0x42460000, 0, 0);
+ trdc_mbc_control_dump(0x42460000, 1, 0);
+
+ for (i = 0; i < 15; i++) {
+ trdc_mbc_mem_dump(0x42460000, 0, 3, 0, i);
+ }
+ trdc_mbc_mem_dump(0x42460000, 0, 3, 1, 0);
+ trdc_mbc_mem_dump(0x42460000, 0, 3, 2, 0);
+
+ for (i = 0; i < 2; i++) {
+ trdc_mbc_mem_dump(0x42460000, 1, 3, 0, i);
+ }
+ trdc_mbc_mem_dump(0x42460000, 1, 3, 1, 0);
+ trdc_mbc_mem_dump(0x42460000, 1, 3, 2, 0);
+ trdc_mbc_mem_dump(0x42460000, 1, 3, 3, 0);
+
+ printf("TRDC NICMIX MBC\n");
+
+ trdc_mbc_control_dump(0x49010000, 0, 0);
+ trdc_mbc_control_dump(0x49010000, 1, 0);
+ trdc_mbc_control_dump(0x49010000, 2, 0);
+ trdc_mbc_control_dump(0x49010000, 3, 0);
+
+ for (i = 0; i < 7; i++) {
+ trdc_mbc_mem_dump(0x49010000, 0, 3, 0, i);
+ }
+
+ for (i = 0; i < 2; i++) {
+ trdc_mbc_mem_dump(0x49010000, 0, 3, 1, i);
+ }
+
+ for (i = 0; i < 5; i++) {
+ trdc_mbc_mem_dump(0x49010000, 0, 3, 2, i);
+ }
+
+ for (i = 0; i < 6; i++) {
+ trdc_mbc_mem_dump(0x49010000, 0, 3, 3, i);
+ }
+
+ for (i = 0; i < 1; i++) {
+ trdc_mbc_mem_dump(0x49010000, 1, 3, 0, i);
+ }
+
+ for (i = 0; i < 1; i++) {
+ trdc_mbc_mem_dump(0x49010000, 1, 3, 1, i);
+ }
+
+ for (i = 0; i < 3; i++) {
+ trdc_mbc_mem_dump(0x49010000, 1, 3, 2, i);
+ }
+
+ for (i = 0; i < 3; i++) {
+ trdc_mbc_mem_dump(0x49010000, 1, 3, 3, i);
+ }
+
+ for (i = 0; i < 2; i++) {
+ trdc_mbc_mem_dump(0x49010000, 2, 3, 0, i);
+ }
+
+ for (i = 0; i < 2; i++) {
+ trdc_mbc_mem_dump(0x49010000, 2, 3, 1, i);
+ }
+
+ for (i = 0; i < 5; i++) {
+ trdc_mbc_mem_dump(0x49010000, 3, 3, 0, i);
+ }
+
+ for (i = 0; i < 5; i++) {
+ trdc_mbc_mem_dump(0x49010000, 3, 3, 1, i);
+ }
+}
+#endif
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 3e538754d9..9bf16119c2 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -31,6 +31,8 @@
#include <hang.h>
#include <cpu_func.h>
#include <env.h>
+#include<dm/device-internal.h>
+#include<dm/lists.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -1005,6 +1007,20 @@ int arch_misc_init(void)
if (ret)
printf("Failed to initialize caam_jr: %d\n", ret);
}
+
+ if (IS_ENABLED(CONFIG_FSL_DCP_RNG)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = device_bind_driver(NULL, "dcp_rng", "dcp_rng", NULL);
+ if (ret)
+ printf("Couldn't bind dcp rng driver (%d)\n", ret);
+
+ ret = uclass_get_device_by_driver(UCLASS_RNG, DM_DRIVER_GET(dcp_rng), &dev);
+ if (ret)
+ printf("Failed to initialize dcp rng: %d\n", ret);
+ }
+
setup_serial_number();
return 0;
}
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index ea709d15a5..919eb6180e 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -148,7 +148,7 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_NONE;
}
-#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
+#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || defined(CONFIG_IMX9)
/* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */
u32 spl_boot_device(void)
{
diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c
index ff4a87132b..d619f1e5d9 100644
--- a/arch/arm/mach-imx/spl_imx_romapi.c
+++ b/arch/arm/mach-imx/spl_imx_romapi.c
@@ -408,10 +408,12 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
{
volatile gd_t *pgd = gd;
int ret;
- u32 boot;
+ u32 boot, bstage;
ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
((uintptr_t)&boot) ^ QUERY_BT_DEV);
+ ret |= g_rom_api->query_boot_infor(QUERY_BT_STAGE, &bstage,
+ ((uintptr_t)&bstage) ^ QUERY_BT_STAGE);
set_gd(pgd);
if (ret != ROM_API_OKAY) {
@@ -419,6 +421,25 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
return -1;
}
+ printf("Boot Stage: ");
+
+ switch (bstage) {
+ case BT_STAGE_PRIMARY:
+ printf("Primary boot\n");
+ break;
+ case BT_STAGE_SECONDARY:
+ printf("Secondary boot\n");
+ break;
+ case BT_STAGE_RECOVERY:
+ printf("Recovery boot\n");
+ break;
+ case BT_STAGE_USB:
+ printf("USB boot\n");
+ break;
+ default:
+ printf("Unknow (0x%x)\n", bstage);
+ }
+
if (is_boot_from_stream_device(boot))
return spl_romapi_load_image_stream(spl_image, bootdev);
diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig
index 77d5ca722c..f4ceb21469 100644
--- a/board/freescale/common/Kconfig
+++ b/board/freescale/common/Kconfig
@@ -3,6 +3,7 @@ config CHAIN_OF_TRUST
imply CMD_BLOB
imply CMD_HASH if ARM
select FSL_CAAM
+ select ARCH_MISC_INIT
select SPL_BOARD_INIT if (ARM && SPL)
select SPL_HASH if (ARM && SPL)
select SHA_HW_ACCEL
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 6f1a0ca91b..18854df253 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -68,7 +68,7 @@ obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o
obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o
obj-$(CONFIG_MXC_EPDC) += epdc_setup.o
-ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 mx7ulp imx8 imx8m vf610 imx8ulp))
+ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 mx7ulp imx8 imx8m vf610 imx8ulp imx9))
obj-y += mmc.o
endif
ifdef CONFIG_FSL_FASTBOOT
diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index 7ffb315bc9..1b9733cf83 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2022 NXP
*/
#include <common.h>
@@ -113,11 +114,6 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr)
fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
#endif
-#ifdef CONFIG_FSL_CAAM
- if (sec_init() < 0)
- fsl_secboot_handle_error(ERROR_ESBC_SEC_INIT);
-#endif
-
/*
* dm_init_and_scan() is called as part of common SPL framework, so no
* need to call it again but in case of powerpc platforms which currently
diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index 34875d0b8f..569a8c4655 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
- * Copyright 2021 NXP
+ * Copyright 2021-2022 NXP
*/
#include <common.h>
@@ -20,6 +20,7 @@
#ifdef CONFIG_ARCH_LS1021A
#include <asm/arch/immap_ls102xa.h>
#endif
+#include <dm/lists.h>
#define SHA256_BITS 256
#define SHA256_BYTES (256/8)
@@ -806,6 +807,13 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img)
prop.num_bits = key_len * 8;
prop.exp_len = key_len;
+#if defined(CONFIG_SPL_BUILD)
+ ret = device_bind_driver(NULL, "fsl_rsa_mod_exp", "fsl_rsa_mod_exp", NULL);
+ if (ret) {
+ printf("Couldn't bind fsl_rsa_mod_exp driver (%d)\n", ret);
+ return -EINVAL;
+ }
+#endif
ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev);
if (ret) {
printf("RSA: Can't find Modular Exp implementation\n");
diff --git a/board/freescale/common/tcpc.c b/board/freescale/common/tcpc.c
index f7d5d328fa..3726ba978b 100644
--- a/board/freescale/common/tcpc.c
+++ b/board/freescale/common/tcpc.c
@@ -35,7 +35,7 @@ int tcpc_set_cc_to_source(struct tcpc_port *port)
uint8_t valb;
int err;
- if (port == NULL)
+ if (port == NULL || port->i2c_dev == NULL)
return -EINVAL;
valb = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
@@ -54,7 +54,7 @@ int tcpc_set_cc_to_sink(struct tcpc_port *port)
uint8_t valb;
int err;
- if (port == NULL)
+ if (port == NULL || port->i2c_dev == NULL)
return -EINVAL;
valb = (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) |
@@ -72,7 +72,7 @@ int tcpc_set_plug_orientation(struct tcpc_port *port, enum typec_cc_polarity pol
uint8_t valb;
int err;
- if (port == NULL)
+ if (port == NULL || port->i2c_dev == NULL)
return -EINVAL;
err = dm_i2c_read(port->i2c_dev, TCPC_TCPC_CTRL, &valb, 1);
@@ -101,7 +101,7 @@ int tcpc_get_cc_status(struct tcpc_port *port, enum typec_cc_polarity *polarity,
uint8_t valb_cc, cc2, cc1;
int err;
- if (port == NULL || polarity == NULL || state == NULL)
+ if (port == NULL || port->i2c_dev == NULL || polarity == NULL || state == NULL)
return -EINVAL;
err = dm_i2c_read(port->i2c_dev, TCPC_CC_STATUS, (uint8_t *)&valb_cc, 1);
@@ -220,7 +220,7 @@ int tcpc_clear_alert(struct tcpc_port *port, uint16_t clear_mask)
{
int err;
- if (port == NULL)
+ if (port == NULL || port->i2c_dev == NULL)
return -EINVAL;
err = dm_i2c_write(port->i2c_dev, TCPC_ALERT, (const uint8_t *)&clear_mask, 2);
@@ -236,7 +236,7 @@ int tcpc_fault_status_mask(struct tcpc_port *port, uint8_t fault_mask)
{
int err = 0;
- if (!port)
+ if (!port || port->i2c_dev == NULL)
return -EINVAL;
err = dm_i2c_write(port->i2c_dev, TCPC_FAULT_STATUS_MASK, &fault_mask, 1);
@@ -250,7 +250,7 @@ int tcpc_send_command(struct tcpc_port *port, uint8_t command)
{
int err;
- if (port == NULL)
+ if (port == NULL || port->i2c_dev == NULL)
return -EINVAL;
err = dm_i2c_write(port->i2c_dev, TCPC_COMMAND, (const uint8_t *)&command, 1);
@@ -269,7 +269,7 @@ int tcpc_polling_reg(struct tcpc_port *port, uint8_t reg,
int err;
ulong start;
- if (port == NULL)
+ if (port == NULL || port->i2c_dev == NULL)
return -EINVAL;
tcpc_debug_log(port, "%s reg 0x%x, mask 0x%x, value 0x%x\n", __func__, reg, mask, value);
@@ -310,7 +310,7 @@ int tcpc_setup_dfp_mode(struct tcpc_port *port)
enum typec_cc_state state;
int ret;
- if ((port == NULL) || (port->i2c_dev == NULL))
+ if (port == NULL)
return -EINVAL;
if (tcpc_pd_sink_check_charging(port)) {
@@ -377,7 +377,7 @@ int tcpc_setup_ufp_mode(struct tcpc_port *port)
enum typec_cc_state state;
int ret;
- if ((port == NULL) || (port->i2c_dev == NULL))
+ if (port == NULL)
return -EINVAL;
/* Check if the PD charge is working. If not, need to configure CC role for UFP */
@@ -477,7 +477,7 @@ static int tcpc_pd_receive_message(struct tcpc_port *port, struct pd_message *ms
uint8_t cnt;
uint16_t val;
- if (port == NULL)
+ if (port == NULL || port->i2c_dev == NULL)
return -EINVAL;
/* Generally the max tSenderResponse is 30ms, max tTypeCSendSourceCap is 200ms, we set the timeout to 500ms */
@@ -514,7 +514,7 @@ static int tcpc_pd_transmit_message(struct tcpc_port *port, struct pd_message *m
uint8_t valb;
uint16_t val = 0;
- if (port == NULL)
+ if (port == NULL || port->i2c_dev == NULL)
return -EINVAL;
if (msg_p == NULL || bytes <= 0)
@@ -796,7 +796,7 @@ bool tcpc_pd_sink_check_charging(struct tcpc_port *port)
enum typec_cc_polarity pol;
enum typec_cc_state state;
- if (port == NULL)
+ if (port == NULL || port->i2c_dev == NULL)
return false;
/* Check the CC status, must be sink */
@@ -834,7 +834,7 @@ static int tcpc_pd_sink_disable(struct tcpc_port *port)
uint8_t valb;
int err;
- if (port == NULL)
+ if (port == NULL || port->i2c_dev == NULL)
return -EINVAL;
port->pd_state = UNATTACH;
@@ -877,7 +877,7 @@ static int tcpc_pd_sink_init(struct tcpc_port *port)
enum typec_cc_polarity pol;
enum typec_cc_state state;
- if (port == NULL)
+ if (port == NULL || port->i2c_dev == NULL)
return -EINVAL;
port->pd_state = UNATTACH;
diff --git a/board/freescale/imx8dxl_evk/spl.c b/board/freescale/imx8dxl_evk/spl.c
index cb78ecf512..fdf966919d 100644
--- a/board/freescale/imx8dxl_evk/spl.c
+++ b/board/freescale/imx8dxl_evk/spl.c
@@ -27,11 +27,7 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
case MMC1_BOOT:
return BOOT_DEVICE_MMC1;
case SD2_BOOT:
-#ifdef CONFIG_TARGET_IMX8DXL_DDR3_EVK
- return BOOT_DEVICE_MMC1;
-#else
return BOOT_DEVICE_MMC2_2;
-#endif
case FLEXSPI_BOOT:
return BOOT_DEVICE_SPI;
case NAND_BOOT:
diff --git a/board/freescale/imx8mm_ab2/Kconfig b/board/freescale/imx8mm_ab2/Kconfig
new file mode 100644
index 0000000000..dbc7cbbebf
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/Kconfig
@@ -0,0 +1,29 @@
+if TARGET_IMX8MM_AB2 || TARGET_IMX8MM_DDR4_AB2 || \
+ TARGET_IMX8MN_AB2 || TARGET_IMX8MN_DDR4_AB2 || \
+ TARGET_IMX8MN_DDR3L_AB2
+
+config SYS_BOARD
+ default "imx8mm_ab2"
+
+config SYS_VENDOR
+ default "freescale"
+
+if IMX8MM
+config SYS_CONFIG_NAME
+ default "imx8mm_ab2"
+
+config IMX_CONFIG
+ default "board/freescale/imx8mm_ab2/imximage-8mm.cfg"
+endif
+
+if IMX8MN
+config SYS_CONFIG_NAME
+ default "imx8mn_ab2"
+
+config IMX_CONFIG
+ default "board/freescale/imx8mm_ab2/imximage-8mn.cfg"
+endif
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/imx8mm_ab2/MAINTAINERS b/board/freescale/imx8mm_ab2/MAINTAINERS
new file mode 100644
index 0000000000..a8b847bcd2
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/MAINTAINERS
@@ -0,0 +1,8 @@
+i.MX8M Mini and Nano Audio Board 2.0
+M: Adrian Alonso <adrian.alonso@nxp.com>
+S: Maintained
+F: board/freescale/imx8mm_ab2/
+F: include/configs/imx8mm_ab2.h
+F: include/configs/imx8mn_ab2.h
+F: configs/imx8mm_ab2_defconfig
+F: configs/imx8mn_ab2_defconfig
diff --git a/board/freescale/imx8mm_ab2/Makefile b/board/freescale/imx8mm_ab2/Makefile
new file mode 100644
index 0000000000..0a540e2a1c
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/Makefile
@@ -0,0 +1,21 @@
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8mm_ab2.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_TARGET_IMX8MM_AB2) += lpddr4_imx8mm_som.o
+obj-$(CONFIG_TARGET_IMX8MM_DDR4_AB2) += ddr4_imx8mm_som.o
+ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
+obj-$(CONFIG_TARGET_IMX8MN_AB2) += lpddr4_imx8mn_som_ld.o
+obj-$(CONFIG_TARGET_IMX8MN_DDR4_AB2) += ddr4_imx8mn_som_ld.o
+else
+obj-$(CONFIG_TARGET_IMX8MN_AB2) += lpddr4_imx8mn_som.o
+obj-$(CONFIG_TARGET_IMX8MN_DDR4_AB2) += ddr4_imx8mn_som.o
+obj-$(CONFIG_TARGET_IMX8MN_DDR3L_AB2) += ddr3l_imx8mn_som.o
+endif
+endif
diff --git a/board/freescale/imx8mm_ab2/ddr3l_imx8mn_som.c b/board/freescale/imx8mm_ab2/ddr3l_imx8mn_som.c
new file mode 100644
index 0000000000..14d18cb491
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/ddr3l_imx8mn_som.c
@@ -0,0 +1,944 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
+ * For imx_v2019.04_5.4.x and above version:
+ * please replace #include <asm/arch/imx8m_ddr.h> with #include <asm/arch/ddr.h>
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x20 },
+ { 0x3d400000, 0xa1040001 },
+ { 0x3d400064, 0x61008c },
+ { 0x3d4000d0, 0xc00200c5 },
+ { 0x3d4000d4, 0x1000b },
+ { 0x3d4000dc, 0x1d700004 },
+ { 0x3d4000e0, 0x180000 },
+ { 0x3d4000e4, 0x90000 },
+ { 0x3d4000f0, 0x0 },
+ { 0x3d4000f4, 0xee5 },
+ { 0x3d400100, 0xc101b0e },
+ { 0x3d400104, 0x30314 },
+ { 0x3d400108, 0x4060509 },
+ { 0x3d40010c, 0x2006 },
+ { 0x3d400110, 0x6020306 },
+ { 0x3d400114, 0x4040302 },
+ { 0x3d400120, 0x909 },
+ { 0x3d400180, 0x40800020 },
+ { 0x3d400184, 0xc350 },
+ { 0x3d400190, 0x3868203 },
+ { 0x3d400194, 0x20303 },
+ { 0x3d4001b4, 0x603 },
+ { 0x3d400198, 0x7000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001a0, 0x400018 },
+ { 0x3d4001a4, 0x5003c },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001c4, 0x0 },
+ { 0x3d400200, 0x1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400208, 0x0 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d400240, 0x600060c },
+ { 0x3d400244, 0x1323 },
+ { 0x3d400400, 0x100 },
+ { 0x3d400250, 0x7ab50b07 },
+ { 0x3d400254, 0x22 },
+ { 0x3d40025c, 0x7b00665e },
+ { 0x3d400264, 0xb0000040 },
+ { 0x3d40026c, 0x50000a0c },
+ { 0x3d400300, 0x17 },
+ { 0x3d40036c, 0x10000 },
+ { 0x3d400404, 0x3051 },
+ { 0x3d400408, 0x61d2 },
+ { 0x3d400494, 0xe00 },
+ { 0x3d400498, 0x7ff },
+ { 0x3d40049c, 0xe00 },
+ { 0x3d4004a0, 0x7ff },
+ { 0x3d402064, 0x28003b },
+ { 0x3d4020dc, 0x12200004 },
+ { 0x3d4020e0, 0x0 },
+ { 0x3d402100, 0x7090b07 },
+ { 0x3d402104, 0x20209 },
+ { 0x3d402108, 0x3030407 },
+ { 0x3d40210c, 0x2006 },
+ { 0x3d402110, 0x3020203 },
+ { 0x3d402114, 0x3030202 },
+ { 0x3d402120, 0x909 },
+ { 0x3d402180, 0x40800020 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x20303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d402240, 0x6000604 },
+ { 0x3d4020f4, 0xee5 },
+ { 0x3d400028, 0x1 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x1005f, 0x3ff },
+ { 0x1015f, 0x3ff },
+ { 0x1105f, 0x3ff },
+ { 0x1115f, 0x3ff },
+ { 0x11005f, 0x3ff },
+ { 0x11015f, 0x3ff },
+ { 0x11105f, 0x3ff },
+ { 0x11115f, 0x3ff },
+ { 0x55, 0x3ff },
+ { 0x1055, 0x3ff },
+ { 0x2055, 0x3ff },
+ { 0x3055, 0x3ff },
+ { 0x4055, 0xff },
+ { 0x5055, 0xff },
+ { 0x6055, 0x3ff },
+ { 0x7055, 0x3ff },
+ { 0x8055, 0x3ff },
+ { 0x9055, 0x3ff },
+ { 0x200c5, 0xb },
+ { 0x1200c5, 0x7 },
+ { 0x2002e, 0x1 },
+ { 0x12002e, 0x1 },
+ { 0x20024, 0x0 },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x0 },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0xa },
+ { 0x120056, 0xa },
+ { 0x1004d, 0x208 },
+ { 0x1014d, 0x208 },
+ { 0x1104d, 0x208 },
+ { 0x1114d, 0x208 },
+ { 0x11004d, 0x208 },
+ { 0x11014d, 0x208 },
+ { 0x11104d, 0x208 },
+ { 0x11114d, 0x208 },
+ { 0x10049, 0xe38 },
+ { 0x10149, 0xe38 },
+ { 0x11049, 0xe38 },
+ { 0x11149, 0xe38 },
+ { 0x110049, 0xe38 },
+ { 0x110149, 0xe38 },
+ { 0x111049, 0xe38 },
+ { 0x111149, 0xe38 },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x1 },
+ { 0x20075, 0x0 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x190 },
+ { 0x120008, 0xa7 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x32c },
+ { 0x10043, 0x581 },
+ { 0x10143, 0x581 },
+ { 0x11043, 0x581 },
+ { 0x11143, 0x581 },
+ { 0x1200b2, 0x32c },
+ { 0x110043, 0x581 },
+ { 0x110143, 0x581 },
+ { 0x111043, 0x581 },
+ { 0x111143, 0x581 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x20019, 0x5 },
+ { 0x120019, 0x5 },
+ { 0x200f0, 0x5555 },
+ { 0x200f1, 0x5555 },
+ { 0x200f2, 0x5555 },
+ { 0x200f3, 0x5555 },
+ { 0x200f4, 0x5555 },
+ { 0x200f5, 0x5555 },
+ { 0x200f6, 0x5555 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x0200b2,0x0},
+ {0x1200b2,0x0},
+ {0x2200b2,0x0},
+ {0x0200cb,0x0},
+ {0x010043,0x0},
+ {0x110043,0x0},
+ {0x210043,0x0},
+ {0x010143,0x0},
+ {0x110143,0x0},
+ {0x210143,0x0},
+ {0x011043,0x0},
+ {0x111043,0x0},
+ {0x211043,0x0},
+ {0x011143,0x0},
+ {0x111143,0x0},
+ {0x211143,0x0},
+ {0x000080,0x0},
+ {0x100080,0x0},
+ {0x200080,0x0},
+ {0x001080,0x0},
+ {0x101080,0x0},
+ {0x201080,0x0},
+ {0x002080,0x0},
+ {0x102080,0x0},
+ {0x202080,0x0},
+ {0x003080,0x0},
+ {0x103080,0x0},
+ {0x203080,0x0},
+ {0x004080,0x0},
+ {0x104080,0x0},
+ {0x204080,0x0},
+ {0x005080,0x0},
+ {0x105080,0x0},
+ {0x205080,0x0},
+ {0x006080,0x0},
+ {0x106080,0x0},
+ {0x206080,0x0},
+ {0x007080,0x0},
+ {0x107080,0x0},
+ {0x207080,0x0},
+ {0x008080,0x0},
+ {0x108080,0x0},
+ {0x208080,0x0},
+ {0x009080,0x0},
+ {0x109080,0x0},
+ {0x209080,0x0},
+ {0x010080,0x0},
+ {0x110080,0x0},
+ {0x210080,0x0},
+ {0x010180,0x0},
+ {0x110180,0x0},
+ {0x210180,0x0},
+ {0x010081,0x0},
+ {0x110081,0x0},
+ {0x210081,0x0},
+ {0x010181,0x0},
+ {0x110181,0x0},
+ {0x210181,0x0},
+ {0x010082,0x0},
+ {0x110082,0x0},
+ {0x210082,0x0},
+ {0x010182,0x0},
+ {0x110182,0x0},
+ {0x210182,0x0},
+ {0x010083,0x0},
+ {0x110083,0x0},
+ {0x210083,0x0},
+ {0x010183,0x0},
+ {0x110183,0x0},
+ {0x210183,0x0},
+ {0x011080,0x0},
+ {0x111080,0x0},
+ {0x211080,0x0},
+ {0x011180,0x0},
+ {0x111180,0x0},
+ {0x211180,0x0},
+ {0x011081,0x0},
+ {0x111081,0x0},
+ {0x211081,0x0},
+ {0x011181,0x0},
+ {0x111181,0x0},
+ {0x211181,0x0},
+ {0x011082,0x0},
+ {0x111082,0x0},
+ {0x211082,0x0},
+ {0x011182,0x0},
+ {0x111182,0x0},
+ {0x211182,0x0},
+ {0x011083,0x0},
+ {0x111083,0x0},
+ {0x211083,0x0},
+ {0x011183,0x0},
+ {0x111183,0x0},
+ {0x211183,0x0},
+ {0x0100d0,0x0},
+ {0x1100d0,0x0},
+ {0x2100d0,0x0},
+ {0x0101d0,0x0},
+ {0x1101d0,0x0},
+ {0x2101d0,0x0},
+ {0x0100d1,0x0},
+ {0x1100d1,0x0},
+ {0x2100d1,0x0},
+ {0x0101d1,0x0},
+ {0x1101d1,0x0},
+ {0x2101d1,0x0},
+ {0x0100d2,0x0},
+ {0x1100d2,0x0},
+ {0x2100d2,0x0},
+ {0x0101d2,0x0},
+ {0x1101d2,0x0},
+ {0x2101d2,0x0},
+ {0x0100d3,0x0},
+ {0x1100d3,0x0},
+ {0x2100d3,0x0},
+ {0x0101d3,0x0},
+ {0x1101d3,0x0},
+ {0x2101d3,0x0},
+ {0x0110d0,0x0},
+ {0x1110d0,0x0},
+ {0x2110d0,0x0},
+ {0x0111d0,0x0},
+ {0x1111d0,0x0},
+ {0x2111d0,0x0},
+ {0x0110d1,0x0},
+ {0x1110d1,0x0},
+ {0x2110d1,0x0},
+ {0x0111d1,0x0},
+ {0x1111d1,0x0},
+ {0x2111d1,0x0},
+ {0x0110d2,0x0},
+ {0x1110d2,0x0},
+ {0x2110d2,0x0},
+ {0x0111d2,0x0},
+ {0x1111d2,0x0},
+ {0x2111d2,0x0},
+ {0x0110d3,0x0},
+ {0x1110d3,0x0},
+ {0x2110d3,0x0},
+ {0x0111d3,0x0},
+ {0x1111d3,0x0},
+ {0x2111d3,0x0},
+ {0x010068,0x0},
+ {0x010168,0x0},
+ {0x010268,0x0},
+ {0x010368,0x0},
+ {0x010468,0x0},
+ {0x010568,0x0},
+ {0x010668,0x0},
+ {0x010768,0x0},
+ {0x010868,0x0},
+ {0x010069,0x0},
+ {0x010169,0x0},
+ {0x010269,0x0},
+ {0x010369,0x0},
+ {0x010469,0x0},
+ {0x010569,0x0},
+ {0x010669,0x0},
+ {0x010769,0x0},
+ {0x010869,0x0},
+ {0x01006a,0x0},
+ {0x01016a,0x0},
+ {0x01026a,0x0},
+ {0x01036a,0x0},
+ {0x01046a,0x0},
+ {0x01056a,0x0},
+ {0x01066a,0x0},
+ {0x01076a,0x0},
+ {0x01086a,0x0},
+ {0x01006b,0x0},
+ {0x01016b,0x0},
+ {0x01026b,0x0},
+ {0x01036b,0x0},
+ {0x01046b,0x0},
+ {0x01056b,0x0},
+ {0x01066b,0x0},
+ {0x01076b,0x0},
+ {0x01086b,0x0},
+ {0x011068,0x0},
+ {0x011168,0x0},
+ {0x011268,0x0},
+ {0x011368,0x0},
+ {0x011468,0x0},
+ {0x011568,0x0},
+ {0x011668,0x0},
+ {0x011768,0x0},
+ {0x011868,0x0},
+ {0x011069,0x0},
+ {0x011169,0x0},
+ {0x011269,0x0},
+ {0x011369,0x0},
+ {0x011469,0x0},
+ {0x011569,0x0},
+ {0x011669,0x0},
+ {0x011769,0x0},
+ {0x011869,0x0},
+ {0x01106a,0x0},
+ {0x01116a,0x0},
+ {0x01126a,0x0},
+ {0x01136a,0x0},
+ {0x01146a,0x0},
+ {0x01156a,0x0},
+ {0x01166a,0x0},
+ {0x01176a,0x0},
+ {0x01186a,0x0},
+ {0x01106b,0x0},
+ {0x01116b,0x0},
+ {0x01126b,0x0},
+ {0x01136b,0x0},
+ {0x01146b,0x0},
+ {0x01156b,0x0},
+ {0x01166b,0x0},
+ {0x01176b,0x0},
+ {0x01186b,0x0},
+ {0x01008c,0x0},
+ {0x11008c,0x0},
+ {0x21008c,0x0},
+ {0x01018c,0x0},
+ {0x11018c,0x0},
+ {0x21018c,0x0},
+ {0x01008d,0x0},
+ {0x11008d,0x0},
+ {0x21008d,0x0},
+ {0x01018d,0x0},
+ {0x11018d,0x0},
+ {0x21018d,0x0},
+ {0x01008e,0x0},
+ {0x11008e,0x0},
+ {0x21008e,0x0},
+ {0x01018e,0x0},
+ {0x11018e,0x0},
+ {0x21018e,0x0},
+ {0x01008f,0x0},
+ {0x11008f,0x0},
+ {0x21008f,0x0},
+ {0x01018f,0x0},
+ {0x11018f,0x0},
+ {0x21018f,0x0},
+ {0x01108c,0x0},
+ {0x11108c,0x0},
+ {0x21108c,0x0},
+ {0x01118c,0x0},
+ {0x11118c,0x0},
+ {0x21118c,0x0},
+ {0x01108d,0x0},
+ {0x11108d,0x0},
+ {0x21108d,0x0},
+ {0x01118d,0x0},
+ {0x11118d,0x0},
+ {0x21118d,0x0},
+ {0x01108e,0x0},
+ {0x11108e,0x0},
+ {0x21108e,0x0},
+ {0x01118e,0x0},
+ {0x11118e,0x0},
+ {0x21118e,0x0},
+ {0x01108f,0x0},
+ {0x11108f,0x0},
+ {0x21108f,0x0},
+ {0x01118f,0x0},
+ {0x11118f,0x0},
+ {0x21118f,0x0},
+ {0x0100c0,0x0},
+ {0x1100c0,0x0},
+ {0x2100c0,0x0},
+ {0x0101c0,0x0},
+ {0x1101c0,0x0},
+ {0x2101c0,0x0},
+ {0x0102c0,0x0},
+ {0x1102c0,0x0},
+ {0x2102c0,0x0},
+ {0x0103c0,0x0},
+ {0x1103c0,0x0},
+ {0x2103c0,0x0},
+ {0x0104c0,0x0},
+ {0x1104c0,0x0},
+ {0x2104c0,0x0},
+ {0x0105c0,0x0},
+ {0x1105c0,0x0},
+ {0x2105c0,0x0},
+ {0x0106c0,0x0},
+ {0x1106c0,0x0},
+ {0x2106c0,0x0},
+ {0x0107c0,0x0},
+ {0x1107c0,0x0},
+ {0x2107c0,0x0},
+ {0x0108c0,0x0},
+ {0x1108c0,0x0},
+ {0x2108c0,0x0},
+ {0x0100c1,0x0},
+ {0x1100c1,0x0},
+ {0x2100c1,0x0},
+ {0x0101c1,0x0},
+ {0x1101c1,0x0},
+ {0x2101c1,0x0},
+ {0x0102c1,0x0},
+ {0x1102c1,0x0},
+ {0x2102c1,0x0},
+ {0x0103c1,0x0},
+ {0x1103c1,0x0},
+ {0x2103c1,0x0},
+ {0x0104c1,0x0},
+ {0x1104c1,0x0},
+ {0x2104c1,0x0},
+ {0x0105c1,0x0},
+ {0x1105c1,0x0},
+ {0x2105c1,0x0},
+ {0x0106c1,0x0},
+ {0x1106c1,0x0},
+ {0x2106c1,0x0},
+ {0x0107c1,0x0},
+ {0x1107c1,0x0},
+ {0x2107c1,0x0},
+ {0x0108c1,0x0},
+ {0x1108c1,0x0},
+ {0x2108c1,0x0},
+ {0x0100c2,0x0},
+ {0x1100c2,0x0},
+ {0x2100c2,0x0},
+ {0x0101c2,0x0},
+ {0x1101c2,0x0},
+ {0x2101c2,0x0},
+ {0x0102c2,0x0},
+ {0x1102c2,0x0},
+ {0x2102c2,0x0},
+ {0x0103c2,0x0},
+ {0x1103c2,0x0},
+ {0x2103c2,0x0},
+ {0x0104c2,0x0},
+ {0x1104c2,0x0},
+ {0x2104c2,0x0},
+ {0x0105c2,0x0},
+ {0x1105c2,0x0},
+ {0x2105c2,0x0},
+ {0x0106c2,0x0},
+ {0x1106c2,0x0},
+ {0x2106c2,0x0},
+ {0x0107c2,0x0},
+ {0x1107c2,0x0},
+ {0x2107c2,0x0},
+ {0x0108c2,0x0},
+ {0x1108c2,0x0},
+ {0x2108c2,0x0},
+ {0x0100c3,0x0},
+ {0x1100c3,0x0},
+ {0x2100c3,0x0},
+ {0x0101c3,0x0},
+ {0x1101c3,0x0},
+ {0x2101c3,0x0},
+ {0x0102c3,0x0},
+ {0x1102c3,0x0},
+ {0x2102c3,0x0},
+ {0x0103c3,0x0},
+ {0x1103c3,0x0},
+ {0x2103c3,0x0},
+ {0x0104c3,0x0},
+ {0x1104c3,0x0},
+ {0x2104c3,0x0},
+ {0x0105c3,0x0},
+ {0x1105c3,0x0},
+ {0x2105c3,0x0},
+ {0x0106c3,0x0},
+ {0x1106c3,0x0},
+ {0x2106c3,0x0},
+ {0x0107c3,0x0},
+ {0x1107c3,0x0},
+ {0x2107c3,0x0},
+ {0x0108c3,0x0},
+ {0x1108c3,0x0},
+ {0x2108c3,0x0},
+ {0x0110c0,0x0},
+ {0x1110c0,0x0},
+ {0x2110c0,0x0},
+ {0x0111c0,0x0},
+ {0x1111c0,0x0},
+ {0x2111c0,0x0},
+ {0x0112c0,0x0},
+ {0x1112c0,0x0},
+ {0x2112c0,0x0},
+ {0x0113c0,0x0},
+ {0x1113c0,0x0},
+ {0x2113c0,0x0},
+ {0x0114c0,0x0},
+ {0x1114c0,0x0},
+ {0x2114c0,0x0},
+ {0x0115c0,0x0},
+ {0x1115c0,0x0},
+ {0x2115c0,0x0},
+ {0x0116c0,0x0},
+ {0x1116c0,0x0},
+ {0x2116c0,0x0},
+ {0x0117c0,0x0},
+ {0x1117c0,0x0},
+ {0x2117c0,0x0},
+ {0x0118c0,0x0},
+ {0x1118c0,0x0},
+ {0x2118c0,0x0},
+ {0x0110c1,0x0},
+ {0x1110c1,0x0},
+ {0x2110c1,0x0},
+ {0x0111c1,0x0},
+ {0x1111c1,0x0},
+ {0x2111c1,0x0},
+ {0x0112c1,0x0},
+ {0x1112c1,0x0},
+ {0x2112c1,0x0},
+ {0x0113c1,0x0},
+ {0x1113c1,0x0},
+ {0x2113c1,0x0},
+ {0x0114c1,0x0},
+ {0x1114c1,0x0},
+ {0x2114c1,0x0},
+ {0x0115c1,0x0},
+ {0x1115c1,0x0},
+ {0x2115c1,0x0},
+ {0x0116c1,0x0},
+ {0x1116c1,0x0},
+ {0x2116c1,0x0},
+ {0x0117c1,0x0},
+ {0x1117c1,0x0},
+ {0x2117c1,0x0},
+ {0x0118c1,0x0},
+ {0x1118c1,0x0},
+ {0x2118c1,0x0},
+ {0x0110c2,0x0},
+ {0x1110c2,0x0},
+ {0x2110c2,0x0},
+ {0x0111c2,0x0},
+ {0x1111c2,0x0},
+ {0x2111c2,0x0},
+ {0x0112c2,0x0},
+ {0x1112c2,0x0},
+ {0x2112c2,0x0},
+ {0x0113c2,0x0},
+ {0x1113c2,0x0},
+ {0x2113c2,0x0},
+ {0x0114c2,0x0},
+ {0x1114c2,0x0},
+ {0x2114c2,0x0},
+ {0x0115c2,0x0},
+ {0x1115c2,0x0},
+ {0x2115c2,0x0},
+ {0x0116c2,0x0},
+ {0x1116c2,0x0},
+ {0x2116c2,0x0},
+ {0x0117c2,0x0},
+ {0x1117c2,0x0},
+ {0x2117c2,0x0},
+ {0x0118c2,0x0},
+ {0x1118c2,0x0},
+ {0x2118c2,0x0},
+ {0x0110c3,0x0},
+ {0x1110c3,0x0},
+ {0x2110c3,0x0},
+ {0x0111c3,0x0},
+ {0x1111c3,0x0},
+ {0x2111c3,0x0},
+ {0x0112c3,0x0},
+ {0x1112c3,0x0},
+ {0x2112c3,0x0},
+ {0x0113c3,0x0},
+ {0x1113c3,0x0},
+ {0x2113c3,0x0},
+ {0x0114c3,0x0},
+ {0x1114c3,0x0},
+ {0x2114c3,0x0},
+ {0x0115c3,0x0},
+ {0x1115c3,0x0},
+ {0x2115c3,0x0},
+ {0x0116c3,0x0},
+ {0x1116c3,0x0},
+ {0x2116c3,0x0},
+ {0x0117c3,0x0},
+ {0x1117c3,0x0},
+ {0x2117c3,0x0},
+ {0x0118c3,0x0},
+ {0x1118c3,0x0},
+ {0x2118c3,0x0},
+ {0x010020,0x0},
+ {0x110020,0x0},
+ {0x210020,0x0},
+ {0x011020,0x0},
+ {0x111020,0x0},
+ {0x211020,0x0},
+ {0x02007d,0x0},
+ {0x12007d,0x0},
+ {0x22007d,0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x640 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x283c },
+ { 0x54006, 0x140 },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x31f },
+ { 0x5400c, 0xc8 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x1d70 },
+ { 0x54030, 0x4 },
+ { 0x54031, 0x18 },
+ { 0x5403a, 0x1323 },
+ { 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x1 },
+ { 0x54003, 0x29c },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x283c },
+ { 0x54006, 0x140 },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x21f },
+ { 0x5400c, 0xc8 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x1220 },
+ { 0x54030, 0x4 },
+ { 0x5403a, 0x1323 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x2 },
+ { 0x90033, 0x10 },
+ { 0x90034, 0x139 },
+ { 0x90035, 0xb },
+ { 0x90036, 0x7c0 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0x44 },
+ { 0x90039, 0x633 },
+ { 0x9003a, 0x159 },
+ { 0x9003b, 0x14f },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x47 },
+ { 0x9003f, 0x633 },
+ { 0x90040, 0x149 },
+ { 0x90041, 0x4f },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x179 },
+ { 0x90044, 0x8 },
+ { 0x90045, 0xe0 },
+ { 0x90046, 0x109 },
+ { 0x90047, 0x0 },
+ { 0x90048, 0x7c8 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x1 },
+ { 0x9004c, 0x8 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x45a },
+ { 0x9004f, 0x9 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x448 },
+ { 0x90052, 0x109 },
+ { 0x90053, 0x40 },
+ { 0x90054, 0x633 },
+ { 0x90055, 0x179 },
+ { 0x90056, 0x1 },
+ { 0x90057, 0x618 },
+ { 0x90058, 0x109 },
+ { 0x90059, 0x40c0 },
+ { 0x9005a, 0x633 },
+ { 0x9005b, 0x149 },
+ { 0x9005c, 0x8 },
+ { 0x9005d, 0x4 },
+ { 0x9005e, 0x48 },
+ { 0x9005f, 0x4040 },
+ { 0x90060, 0x633 },
+ { 0x90061, 0x149 },
+ { 0x90062, 0x0 },
+ { 0x90063, 0x4 },
+ { 0x90064, 0x48 },
+ { 0x90065, 0x40 },
+ { 0x90066, 0x633 },
+ { 0x90067, 0x149 },
+ { 0x90068, 0x10 },
+ { 0x90069, 0x4 },
+ { 0x9006a, 0x18 },
+ { 0x9006b, 0x0 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x78 },
+ { 0x9006e, 0x549 },
+ { 0x9006f, 0x633 },
+ { 0x90070, 0x159 },
+ { 0x90071, 0xd49 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0x94a },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x441 },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x149 },
+ { 0x9007a, 0x42 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x1 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x0 },
+ { 0x90081, 0xe0 },
+ { 0x90082, 0x109 },
+ { 0x90083, 0xa },
+ { 0x90084, 0x10 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0x9 },
+ { 0x90087, 0x3c0 },
+ { 0x90088, 0x149 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x159 },
+ { 0x9008c, 0x18 },
+ { 0x9008d, 0x10 },
+ { 0x9008e, 0x109 },
+ { 0x9008f, 0x0 },
+ { 0x90090, 0x3c0 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x18 },
+ { 0x90093, 0x4 },
+ { 0x90094, 0x48 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x58 },
+ { 0x90098, 0xb },
+ { 0x90099, 0x10 },
+ { 0x9009a, 0x109 },
+ { 0x9009b, 0x1 },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x5 },
+ { 0x9009f, 0x7c0 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x0 },
+ { 0x900a2, 0x8140 },
+ { 0x900a3, 0x10c },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x8138 },
+ { 0x900a6, 0x10c },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7c8 },
+ { 0x900a9, 0x101 },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x448 },
+ { 0x900ac, 0x109 },
+ { 0x900ad, 0xf },
+ { 0x900ae, 0x7c0 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x47 },
+ { 0x900b1, 0x630 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x8 },
+ { 0x900b4, 0x618 },
+ { 0x900b5, 0x109 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0xe0 },
+ { 0x900b8, 0x109 },
+ { 0x900b9, 0x0 },
+ { 0x900ba, 0x7c8 },
+ { 0x900bb, 0x109 },
+ { 0x900bc, 0x8 },
+ { 0x900bd, 0x8140 },
+ { 0x900be, 0x10c },
+ { 0x900bf, 0x0 },
+ { 0x900c0, 0x1 },
+ { 0x900c1, 0x8 },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x8 },
+ { 0x900c5, 0x8 },
+ { 0x900c6, 0x7c8 },
+ { 0x900c7, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x90026, 0x2b },
+ { 0x2000b, 0x32 },
+ { 0x2000c, 0x64 },
+ { 0x2000d, 0x3e8 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0x14 },
+ { 0x12000c, 0x26 },
+ { 0x12000d, 0x1a1 },
+ { 0x12000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0xffff },
+ { 0x90013, 0x6152 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x0 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 1600mts 1D */
+ .drate = 1600,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 667mts 1D */
+ .drate = 667,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 1600, 667, },
+};
+
diff --git a/board/freescale/imx8mm_ab2/ddr4_imx8mm_som.c b/board/freescale/imx8mm_ab2/ddr4_imx8mm_som.c
new file mode 100644
index 0000000000..2f80b9832b
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/ddr4_imx8mm_som.c
@@ -0,0 +1,1265 @@
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0x81040010 },
+ { 0x3d400030, 0xaa },
+ { 0x3d400034, 0x221306 },
+ { 0x3d400050, 0x210070 },
+ { 0x3d400054, 0x10008 },
+ { 0x3d400060, 0x0 },
+ { 0x3d400064, 0x9200d2 },
+ { 0x3d4000c0, 0x0 },
+ { 0x3d4000c4, 0x1000 },
+ { 0x3d4000d0, 0xc0030126 },
+ { 0x3d4000d4, 0x770000 },
+ { 0x3d4000dc, 0x8340105 },
+ { 0x3d4000e0, 0x180200 },
+ { 0x3d4000e4, 0x110000 },
+ { 0x3d4000e8, 0x2000600 },
+ { 0x3d4000ec, 0x814 },
+ { 0x3d4000f0, 0x20 },
+ { 0x3d4000f4, 0xec7 },
+ { 0x3d400100, 0x11122914 },
+ { 0x3d400104, 0x4051c },
+ { 0x3d400108, 0x608050d },
+ { 0x3d40010c, 0x400c },
+ { 0x3d400110, 0x8030409 },
+ { 0x3d400114, 0x6060403 },
+ { 0x3d40011c, 0x606 },
+ { 0x3d400120, 0x5050d08 },
+ { 0x3d400124, 0x2040a },
+ { 0x3d40012c, 0x1409010e },
+ { 0x3d400130, 0x8 },
+ { 0x3d40013c, 0x0 },
+ { 0x3d400180, 0x1000040 },
+ { 0x3d400184, 0x493e },
+ { 0x3d400190, 0x38b8207 },
+ { 0x3d400194, 0x2020303 },
+ { 0x3d400198, 0x7f04011 },
+ { 0x3d40019c, 0xb0 },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0x48005a },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x1 },
+ { 0x3d4001b4, 0xb07 },
+ { 0x3d4001b8, 0x4 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x0 },
+ { 0x3d400200, 0x3f1f },
+ { 0x3d400204, 0x3f0909 },
+ { 0x3d400208, 0x700 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf0f },
+ { 0x3d400220, 0x3f01 },
+ { 0x3d400240, 0x6000610 },
+ { 0x3d400244, 0x1323 },
+ { 0x3d402050, 0x210070 },
+ { 0x3d402064, 0x40005e },
+ { 0x3d4020dc, 0x40105 },
+ { 0x3d4020e0, 0x0 },
+ { 0x3d4020e8, 0x2000600 },
+ { 0x3d4020ec, 0x14 },
+ { 0x3d402100, 0xb081209 },
+ { 0x3d402104, 0x2020d },
+ { 0x3d402108, 0x5050309 },
+ { 0x3d40210c, 0x400c },
+ { 0x3d402110, 0x4030205 },
+ { 0x3d402114, 0x3030202 },
+ { 0x3d40211c, 0x303 },
+ { 0x3d402120, 0x3030d04 },
+ { 0x3d402124, 0x20208 },
+ { 0x3d40212c, 0x1005010e },
+ { 0x3d402130, 0x8 },
+ { 0x3d40213c, 0x0 },
+ { 0x3d402180, 0x1000040 },
+ { 0x3d402190, 0x3858204 },
+ { 0x3d402194, 0x2020303 },
+ { 0x3d4021b4, 0x504 },
+ { 0x3d4021b8, 0x4 },
+ { 0x3d402240, 0x6000604 },
+ { 0x3d4020f4, 0xec7 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x1005f, 0x2fd },
+ { 0x1015f, 0x2fd },
+ { 0x1105f, 0x2fd },
+ { 0x1115f, 0x2fd },
+ { 0x1205f, 0x2fd },
+ { 0x1215f, 0x2fd },
+ { 0x1305f, 0x2fd },
+ { 0x1315f, 0x2fd },
+ { 0x11005f, 0x2fd },
+ { 0x11015f, 0x2fd },
+ { 0x11105f, 0x2fd },
+ { 0x11115f, 0x2fd },
+ { 0x11205f, 0x2fd },
+ { 0x11215f, 0x2fd },
+ { 0x11305f, 0x2fd },
+ { 0x11315f, 0x2fd },
+ { 0x55, 0x355 },
+ { 0x1055, 0x355 },
+ { 0x2055, 0x355 },
+ { 0x3055, 0x355 },
+ { 0x4055, 0x55 },
+ { 0x5055, 0x55 },
+ { 0x6055, 0x355 },
+ { 0x7055, 0x355 },
+ { 0x8055, 0x355 },
+ { 0x9055, 0x355 },
+ { 0x200c5, 0xa },
+ { 0x1200c5, 0x6 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x1 },
+ { 0x20024, 0x8 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x8 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x6 },
+ { 0x120056, 0xa },
+ { 0x1004d, 0x1a },
+ { 0x1014d, 0x1a },
+ { 0x1104d, 0x1a },
+ { 0x1114d, 0x1a },
+ { 0x1204d, 0x1a },
+ { 0x1214d, 0x1a },
+ { 0x1304d, 0x1a },
+ { 0x1314d, 0x1a },
+ { 0x11004d, 0x1a },
+ { 0x11014d, 0x1a },
+ { 0x11104d, 0x1a },
+ { 0x11114d, 0x1a },
+ { 0x11204d, 0x1a },
+ { 0x11214d, 0x1a },
+ { 0x11304d, 0x1a },
+ { 0x11314d, 0x1a },
+ { 0x10049, 0xe38 },
+ { 0x10149, 0xe38 },
+ { 0x11049, 0xe38 },
+ { 0x11149, 0xe38 },
+ { 0x12049, 0xe38 },
+ { 0x12149, 0xe38 },
+ { 0x13049, 0xe38 },
+ { 0x13149, 0xe38 },
+ { 0x110049, 0xe38 },
+ { 0x110149, 0xe38 },
+ { 0x111049, 0xe38 },
+ { 0x111149, 0xe38 },
+ { 0x112049, 0xe38 },
+ { 0x112149, 0xe38 },
+ { 0x113049, 0xe38 },
+ { 0x113149, 0xe38 },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x5 },
+ { 0x20075, 0x2 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x258 },
+ { 0x120008, 0x10a },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x268 },
+ { 0x10043, 0x5b1 },
+ { 0x10143, 0x5b1 },
+ { 0x11043, 0x5b1 },
+ { 0x11143, 0x5b1 },
+ { 0x12043, 0x5b1 },
+ { 0x12143, 0x5b1 },
+ { 0x13043, 0x5b1 },
+ { 0x13143, 0x5b1 },
+ { 0x1200b2, 0x268 },
+ { 0x110043, 0x5b1 },
+ { 0x110143, 0x5b1 },
+ { 0x111043, 0x5b1 },
+ { 0x111143, 0x5b1 },
+ { 0x112043, 0x5b1 },
+ { 0x112143, 0x5b1 },
+ { 0x113043, 0x5b1 },
+ { 0x113143, 0x5b1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x20019, 0x5 },
+ { 0x120019, 0x5 },
+ { 0x200f0, 0x5555 },
+ { 0x200f1, 0x5555 },
+ { 0x200f2, 0x5555 },
+ { 0x200f3, 0x5555 },
+ { 0x200f4, 0x5555 },
+ { 0x200f5, 0x5555 },
+ { 0x200f6, 0x5555 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x1200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x1200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x960 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x2000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x31f },
+ { 0x5400c, 0xc8 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x834 },
+ { 0x54030, 0x105 },
+ { 0x54031, 0x18 },
+ { 0x54032, 0x200 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x814 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1323 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x1 },
+ { 0x54003, 0x42a },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x2000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x21f },
+ { 0x5400c, 0xc8 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x4 },
+ { 0x54030, 0x105 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x14 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1323 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x960 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x2000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x61 },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x5400e, 0x1f7f },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x834 },
+ { 0x54030, 0x105 },
+ { 0x54031, 0x18 },
+ { 0x54032, 0x200 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x814 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1323 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x2 },
+ { 0x90033, 0x10 },
+ { 0x90034, 0x139 },
+ { 0x90035, 0xf },
+ { 0x90036, 0x7c0 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0x44 },
+ { 0x90039, 0x630 },
+ { 0x9003a, 0x159 },
+ { 0x9003b, 0x14f },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x47 },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x149 },
+ { 0x90041, 0x4f },
+ { 0x90042, 0x630 },
+ { 0x90043, 0x179 },
+ { 0x90044, 0x8 },
+ { 0x90045, 0xe0 },
+ { 0x90046, 0x109 },
+ { 0x90047, 0x0 },
+ { 0x90048, 0x7c8 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x1 },
+ { 0x9004c, 0x8 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x45a },
+ { 0x9004f, 0x9 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x448 },
+ { 0x90052, 0x109 },
+ { 0x90053, 0x40 },
+ { 0x90054, 0x630 },
+ { 0x90055, 0x179 },
+ { 0x90056, 0x1 },
+ { 0x90057, 0x618 },
+ { 0x90058, 0x109 },
+ { 0x90059, 0x40c0 },
+ { 0x9005a, 0x630 },
+ { 0x9005b, 0x149 },
+ { 0x9005c, 0x8 },
+ { 0x9005d, 0x4 },
+ { 0x9005e, 0x48 },
+ { 0x9005f, 0x4040 },
+ { 0x90060, 0x630 },
+ { 0x90061, 0x149 },
+ { 0x90062, 0x0 },
+ { 0x90063, 0x4 },
+ { 0x90064, 0x48 },
+ { 0x90065, 0x40 },
+ { 0x90066, 0x630 },
+ { 0x90067, 0x149 },
+ { 0x90068, 0x10 },
+ { 0x90069, 0x4 },
+ { 0x9006a, 0x18 },
+ { 0x9006b, 0x0 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x78 },
+ { 0x9006e, 0x549 },
+ { 0x9006f, 0x630 },
+ { 0x90070, 0x159 },
+ { 0x90071, 0xd49 },
+ { 0x90072, 0x630 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0x94a },
+ { 0x90075, 0x630 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x441 },
+ { 0x90078, 0x630 },
+ { 0x90079, 0x149 },
+ { 0x9007a, 0x42 },
+ { 0x9007b, 0x630 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x1 },
+ { 0x9007e, 0x630 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x0 },
+ { 0x90081, 0xe0 },
+ { 0x90082, 0x109 },
+ { 0x90083, 0xa },
+ { 0x90084, 0x10 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0x9 },
+ { 0x90087, 0x3c0 },
+ { 0x90088, 0x149 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x159 },
+ { 0x9008c, 0x18 },
+ { 0x9008d, 0x10 },
+ { 0x9008e, 0x109 },
+ { 0x9008f, 0x0 },
+ { 0x90090, 0x3c0 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x18 },
+ { 0x90093, 0x4 },
+ { 0x90094, 0x48 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x58 },
+ { 0x90098, 0xa },
+ { 0x90099, 0x10 },
+ { 0x9009a, 0x109 },
+ { 0x9009b, 0x2 },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x7 },
+ { 0x9009f, 0x7c0 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x10 },
+ { 0x900a2, 0x10 },
+ { 0x900a3, 0x109 },
+ { 0x900a4, 0x0 },
+ { 0x900a5, 0x8140 },
+ { 0x900a6, 0x10c },
+ { 0x900a7, 0x10 },
+ { 0x900a8, 0x8138 },
+ { 0x900a9, 0x10c },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x7c8 },
+ { 0x900ac, 0x101 },
+ { 0x900ad, 0x8 },
+ { 0x900ae, 0x0 },
+ { 0x900af, 0x8 },
+ { 0x900b0, 0x8 },
+ { 0x900b1, 0x448 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0xf },
+ { 0x900b4, 0x7c0 },
+ { 0x900b5, 0x109 },
+ { 0x900b6, 0x47 },
+ { 0x900b7, 0x630 },
+ { 0x900b8, 0x109 },
+ { 0x900b9, 0x8 },
+ { 0x900ba, 0x618 },
+ { 0x900bb, 0x109 },
+ { 0x900bc, 0x8 },
+ { 0x900bd, 0xe0 },
+ { 0x900be, 0x109 },
+ { 0x900bf, 0x0 },
+ { 0x900c0, 0x7c8 },
+ { 0x900c1, 0x109 },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x8140 },
+ { 0x900c4, 0x10c },
+ { 0x900c5, 0x0 },
+ { 0x900c6, 0x1 },
+ { 0x900c7, 0x8 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x4 },
+ { 0x900ca, 0x8 },
+ { 0x900cb, 0x8 },
+ { 0x900cc, 0x7c8 },
+ { 0x900cd, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x90026, 0x2c },
+ { 0x2000b, 0x4b },
+ { 0x2000c, 0x96 },
+ { 0x2000d, 0x5dc },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0x21 },
+ { 0x12000c, 0x42 },
+ { 0x12000d, 0x29a },
+ { 0x12000e, 0x21 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0xffff },
+ { 0x90013, 0x6152 },
+ { 0xc0080, 0x0 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 2400mts 1D */
+ .drate = 2400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 1066mts 1D */
+ .drate = 1066,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P0 2400mts 2D */
+ .drate = 2400,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 2400, 1066, },
+};
diff --git a/board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c b/board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c
new file mode 100644
index 0000000000..84114a3e8a
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c
@@ -0,0 +1,1057 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400000, 0x81040010 },
+ { 0x3d400030, 0x20 },
+ { 0x3d400034, 0x221306 },
+ { 0x3d400050, 0x210070 },
+ { 0x3d400054, 0x10008 },
+ { 0x3d400060, 0x0 },
+ { 0x3d400064, 0x92014a },
+ { 0x3d4000c0, 0x0 },
+ { 0x3d4000c4, 0x1000 },
+ { 0x3d4000d0, 0xc0030126 },
+ { 0x3d4000d4, 0x770000 },
+ { 0x3d4000dc, 0x8340105 },
+ { 0x3d4000e0, 0x180200 },
+ { 0x3d4000e4, 0x110000 },
+ { 0x3d4000e8, 0x2000600 },
+ { 0x3d4000ec, 0x810 },
+ { 0x3d4000f0, 0x20 },
+ { 0x3d4000f4, 0xec7 },
+ { 0x3d400100, 0x11122914 },
+ { 0x3d400104, 0x4051c },
+ { 0x3d400108, 0x608050d },
+ { 0x3d40010c, 0x400c },
+ { 0x3d400110, 0x8030409 },
+ { 0x3d400114, 0x6060403 },
+ { 0x3d40011c, 0x606 },
+ { 0x3d400120, 0x7070d0c },
+ { 0x3d400124, 0x2040a },
+ { 0x3d40012c, 0x1809010e },
+ { 0x3d400130, 0x8 },
+ { 0x3d40013c, 0x0 },
+ { 0x3d400180, 0x1000040 },
+ { 0x3d400184, 0x493e },
+ { 0x3d400190, 0x38b8207 },
+ { 0x3d400194, 0x2020303 },
+ { 0x3d400198, 0x7f04011 },
+ { 0x3d40019c, 0xb0 },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0x48005a },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x1 },
+ { 0x3d4001b4, 0xb07 },
+ { 0x3d4001b8, 0x4 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x0 },
+ { 0x3d400200, 0x3f1f },
+ { 0x3d400204, 0x3f0909 },
+ { 0x3d400208, 0x700 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf07 },
+ { 0x3d400220, 0x3f01 },
+ { 0x3d400240, 0x6000610 },
+ { 0x3d400244, 0x1323 },
+ { 0x3d400400, 0x100 },
+
+ /* performance setting */
+ { 0x3d400250, 0x00001f05 },
+ { 0x3d400254, 0x1f },
+ { 0x3d400264, 0x900003ff },
+ { 0x3d40026c, 0x200003ff },
+ { 0x3d400494, 0x01000e00 },
+ { 0x3d400498, 0x03ff0000 },
+ { 0x3d40049c, 0x01000e00 },
+ { 0x3d4004a0, 0x03ff0000 },
+
+ { 0x3d402050, 0x210070 },
+ { 0x3d402064, 0x400093 },
+ { 0x3d4020dc, 0x105 },
+ { 0x3d4020e0, 0x0 },
+ { 0x3d4020e8, 0x2000600 },
+ { 0x3d4020ec, 0x10 },
+ { 0x3d402100, 0xb081209 },
+ { 0x3d402104, 0x2020d },
+ { 0x3d402108, 0x5050309 },
+ { 0x3d40210c, 0x400c },
+ { 0x3d402110, 0x5030206 },
+ { 0x3d402114, 0x3030202 },
+ { 0x3d40211c, 0x303 },
+ { 0x3d402120, 0x4040d06 },
+ { 0x3d402124, 0x20208 },
+ { 0x3d40212c, 0x1205010e },
+ { 0x3d402130, 0x8 },
+ { 0x3d40213c, 0x0 },
+ { 0x3d402180, 0x1000040 },
+ { 0x3d402190, 0x3848204 },
+ { 0x3d402194, 0x2020303 },
+ { 0x3d4021b4, 0x404 },
+ { 0x3d4021b8, 0x4 },
+ { 0x3d402240, 0x6000600 },
+ { 0x3d4020f4, 0xec7 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x1005f, 0x2fd },
+ { 0x1015f, 0x2fd },
+ { 0x1105f, 0x2fd },
+ { 0x1115f, 0x2fd },
+ { 0x11005f, 0x2fd },
+ { 0x11015f, 0x2fd },
+ { 0x11105f, 0x2fd },
+ { 0x11115f, 0x2fd },
+ { 0x55, 0x355 },
+ { 0x1055, 0x355 },
+ { 0x2055, 0x355 },
+ { 0x3055, 0x355 },
+ { 0x4055, 0x55 },
+ { 0x5055, 0x55 },
+ { 0x6055, 0x355 },
+ { 0x7055, 0x355 },
+ { 0x8055, 0x355 },
+ { 0x9055, 0x355 },
+ { 0x200c5, 0xa },
+ { 0x1200c5, 0x6 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x1 },
+ { 0x20024, 0x8 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x8 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x6 },
+ { 0x120056, 0xa },
+ { 0x1004d, 0x1a },
+ { 0x1014d, 0x1a },
+ { 0x1104d, 0x1a },
+ { 0x1114d, 0x1a },
+ { 0x11004d, 0x1a },
+ { 0x11014d, 0x1a },
+ { 0x11104d, 0x1a },
+ { 0x11114d, 0x1a },
+ { 0x10049, 0xe38 },
+ { 0x10149, 0xe38 },
+ { 0x11049, 0xe38 },
+ { 0x11149, 0xe38 },
+ { 0x110049, 0xe38 },
+ { 0x110149, 0xe38 },
+ { 0x111049, 0xe38 },
+ { 0x111149, 0xe38 },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x1 },
+ { 0x20075, 0x2 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x258 },
+ { 0x120008, 0x10a },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x268 },
+ { 0x10043, 0x5b1 },
+ { 0x10143, 0x5b1 },
+ { 0x11043, 0x5b1 },
+ { 0x11143, 0x5b1 },
+ { 0x1200b2, 0x268 },
+ { 0x110043, 0x5b1 },
+ { 0x110143, 0x5b1 },
+ { 0x111043, 0x5b1 },
+ { 0x111143, 0x5b1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x20019, 0x5 },
+ { 0x120019, 0x5 },
+ { 0x200f0, 0x5555 },
+ { 0x200f1, 0x5555 },
+ { 0x200f2, 0x5555 },
+ { 0x200f3, 0x5555 },
+ { 0x200f4, 0x5555 },
+ { 0x200f5, 0x5555 },
+ { 0x200f6, 0x5555 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x2005b, 0x7529 },
+ { 0x2005c, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x200cc, 0x1f7 },
+ { 0x1200c7, 0x21 },
+ { 0x1200ca, 0x24 },
+ { 0x1200cc, 0x1f7 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x0200b2, 0x0},
+ {0x1200b2, 0x0},
+ {0x2200b2, 0x0},
+ {0x0200cb, 0x0},
+ {0x010043, 0x0},
+ {0x110043, 0x0},
+ {0x210043, 0x0},
+ {0x010143, 0x0},
+ {0x110143, 0x0},
+ {0x210143, 0x0},
+ {0x011043, 0x0},
+ {0x111043, 0x0},
+ {0x211043, 0x0},
+ {0x011143, 0x0},
+ {0x111143, 0x0},
+ {0x211143, 0x0},
+ {0x000080, 0x0},
+ {0x100080, 0x0},
+ {0x200080, 0x0},
+ {0x001080, 0x0},
+ {0x101080, 0x0},
+ {0x201080, 0x0},
+ {0x002080, 0x0},
+ {0x102080, 0x0},
+ {0x202080, 0x0},
+ {0x003080, 0x0},
+ {0x103080, 0x0},
+ {0x203080, 0x0},
+ {0x004080, 0x0},
+ {0x104080, 0x0},
+ {0x204080, 0x0},
+ {0x005080, 0x0},
+ {0x105080, 0x0},
+ {0x205080, 0x0},
+ {0x006080, 0x0},
+ {0x106080, 0x0},
+ {0x206080, 0x0},
+ {0x007080, 0x0},
+ {0x107080, 0x0},
+ {0x207080, 0x0},
+ {0x008080, 0x0},
+ {0x108080, 0x0},
+ {0x208080, 0x0},
+ {0x009080, 0x0},
+ {0x109080, 0x0},
+ {0x209080, 0x0},
+ {0x010080, 0x0},
+ {0x110080, 0x0},
+ {0x210080, 0x0},
+ {0x010180, 0x0},
+ {0x110180, 0x0},
+ {0x210180, 0x0},
+ {0x010081, 0x0},
+ {0x110081, 0x0},
+ {0x210081, 0x0},
+ {0x010181, 0x0},
+ {0x110181, 0x0},
+ {0x210181, 0x0},
+ {0x010082, 0x0},
+ {0x110082, 0x0},
+ {0x210082, 0x0},
+ {0x010182, 0x0},
+ {0x110182, 0x0},
+ {0x210182, 0x0},
+ {0x010083, 0x0},
+ {0x110083, 0x0},
+ {0x210083, 0x0},
+ {0x010183, 0x0},
+ {0x110183, 0x0},
+ {0x210183, 0x0},
+ {0x011080, 0x0},
+ {0x111080, 0x0},
+ {0x211080, 0x0},
+ {0x011180, 0x0},
+ {0x111180, 0x0},
+ {0x211180, 0x0},
+ {0x011081, 0x0},
+ {0x111081, 0x0},
+ {0x211081, 0x0},
+ {0x011181, 0x0},
+ {0x111181, 0x0},
+ {0x211181, 0x0},
+ {0x011082, 0x0},
+ {0x111082, 0x0},
+ {0x211082, 0x0},
+ {0x011182, 0x0},
+ {0x111182, 0x0},
+ {0x211182, 0x0},
+ {0x011083, 0x0},
+ {0x111083, 0x0},
+ {0x211083, 0x0},
+ {0x011183, 0x0},
+ {0x111183, 0x0},
+ {0x211183, 0x0},
+ {0x0100d0, 0x0},
+ {0x1100d0, 0x0},
+ {0x2100d0, 0x0},
+ {0x0101d0, 0x0},
+ {0x1101d0, 0x0},
+ {0x2101d0, 0x0},
+ {0x0100d1, 0x0},
+ {0x1100d1, 0x0},
+ {0x2100d1, 0x0},
+ {0x0101d1, 0x0},
+ {0x1101d1, 0x0},
+ {0x2101d1, 0x0},
+ {0x0100d2, 0x0},
+ {0x1100d2, 0x0},
+ {0x2100d2, 0x0},
+ {0x0101d2, 0x0},
+ {0x1101d2, 0x0},
+ {0x2101d2, 0x0},
+ {0x0100d3, 0x0},
+ {0x1100d3, 0x0},
+ {0x2100d3, 0x0},
+ {0x0101d3, 0x0},
+ {0x1101d3, 0x0},
+ {0x2101d3, 0x0},
+ {0x0110d0, 0x0},
+ {0x1110d0, 0x0},
+ {0x2110d0, 0x0},
+ {0x0111d0, 0x0},
+ {0x1111d0, 0x0},
+ {0x2111d0, 0x0},
+ {0x0110d1, 0x0},
+ {0x1110d1, 0x0},
+ {0x2110d1, 0x0},
+ {0x0111d1, 0x0},
+ {0x1111d1, 0x0},
+ {0x2111d1, 0x0},
+ {0x0110d2, 0x0},
+ {0x1110d2, 0x0},
+ {0x2110d2, 0x0},
+ {0x0111d2, 0x0},
+ {0x1111d2, 0x0},
+ {0x2111d2, 0x0},
+ {0x0110d3, 0x0},
+ {0x1110d3, 0x0},
+ {0x2110d3, 0x0},
+ {0x0111d3, 0x0},
+ {0x1111d3, 0x0},
+ {0x2111d3, 0x0},
+ {0x010068, 0x0},
+ {0x010168, 0x0},
+ {0x010268, 0x0},
+ {0x010368, 0x0},
+ {0x010468, 0x0},
+ {0x010568, 0x0},
+ {0x010668, 0x0},
+ {0x010768, 0x0},
+ {0x010868, 0x0},
+ {0x010069, 0x0},
+ {0x010169, 0x0},
+ {0x010269, 0x0},
+ {0x010369, 0x0},
+ {0x010469, 0x0},
+ {0x010569, 0x0},
+ {0x010669, 0x0},
+ {0x010769, 0x0},
+ {0x010869, 0x0},
+ {0x01006a, 0x0},
+ {0x01016a, 0x0},
+ {0x01026a, 0x0},
+ {0x01036a, 0x0},
+ {0x01046a, 0x0},
+ {0x01056a, 0x0},
+ {0x01066a, 0x0},
+ {0x01076a, 0x0},
+ {0x01086a, 0x0},
+ {0x01006b, 0x0},
+ {0x01016b, 0x0},
+ {0x01026b, 0x0},
+ {0x01036b, 0x0},
+ {0x01046b, 0x0},
+ {0x01056b, 0x0},
+ {0x01066b, 0x0},
+ {0x01076b, 0x0},
+ {0x01086b, 0x0},
+ {0x011068, 0x0},
+ {0x011168, 0x0},
+ {0x011268, 0x0},
+ {0x011368, 0x0},
+ {0x011468, 0x0},
+ {0x011568, 0x0},
+ {0x011668, 0x0},
+ {0x011768, 0x0},
+ {0x011868, 0x0},
+ {0x011069, 0x0},
+ {0x011169, 0x0},
+ {0x011269, 0x0},
+ {0x011369, 0x0},
+ {0x011469, 0x0},
+ {0x011569, 0x0},
+ {0x011669, 0x0},
+ {0x011769, 0x0},
+ {0x011869, 0x0},
+ {0x01106a, 0x0},
+ {0x01116a, 0x0},
+ {0x01126a, 0x0},
+ {0x01136a, 0x0},
+ {0x01146a, 0x0},
+ {0x01156a, 0x0},
+ {0x01166a, 0x0},
+ {0x01176a, 0x0},
+ {0x01186a, 0x0},
+ {0x01106b, 0x0},
+ {0x01116b, 0x0},
+ {0x01126b, 0x0},
+ {0x01136b, 0x0},
+ {0x01146b, 0x0},
+ {0x01156b, 0x0},
+ {0x01166b, 0x0},
+ {0x01176b, 0x0},
+ {0x01186b, 0x0},
+ {0x01008c, 0x0},
+ {0x11008c, 0x0},
+ {0x21008c, 0x0},
+ {0x01018c, 0x0},
+ {0x11018c, 0x0},
+ {0x21018c, 0x0},
+ {0x01008d, 0x0},
+ {0x11008d, 0x0},
+ {0x21008d, 0x0},
+ {0x01018d, 0x0},
+ {0x11018d, 0x0},
+ {0x21018d, 0x0},
+ {0x01008e, 0x0},
+ {0x11008e, 0x0},
+ {0x21008e, 0x0},
+ {0x01018e, 0x0},
+ {0x11018e, 0x0},
+ {0x21018e, 0x0},
+ {0x01008f, 0x0},
+ {0x11008f, 0x0},
+ {0x21008f, 0x0},
+ {0x01018f, 0x0},
+ {0x11018f, 0x0},
+ {0x21018f, 0x0},
+ {0x01108c, 0x0},
+ {0x11108c, 0x0},
+ {0x21108c, 0x0},
+ {0x01118c, 0x0},
+ {0x11118c, 0x0},
+ {0x21118c, 0x0},
+ {0x01108d, 0x0},
+ {0x11108d, 0x0},
+ {0x21108d, 0x0},
+ {0x01118d, 0x0},
+ {0x11118d, 0x0},
+ {0x21118d, 0x0},
+ {0x01108e, 0x0},
+ {0x11108e, 0x0},
+ {0x21108e, 0x0},
+ {0x01118e, 0x0},
+ {0x11118e, 0x0},
+ {0x21118e, 0x0},
+ {0x01108f, 0x0},
+ {0x11108f, 0x0},
+ {0x21108f, 0x0},
+ {0x01118f, 0x0},
+ {0x11118f, 0x0},
+ {0x21118f, 0x0},
+ {0x0100c0, 0x0},
+ {0x1100c0, 0x0},
+ {0x2100c0, 0x0},
+ {0x0101c0, 0x0},
+ {0x1101c0, 0x0},
+ {0x2101c0, 0x0},
+ {0x0102c0, 0x0},
+ {0x1102c0, 0x0},
+ {0x2102c0, 0x0},
+ {0x0103c0, 0x0},
+ {0x1103c0, 0x0},
+ {0x2103c0, 0x0},
+ {0x0104c0, 0x0},
+ {0x1104c0, 0x0},
+ {0x2104c0, 0x0},
+ {0x0105c0, 0x0},
+ {0x1105c0, 0x0},
+ {0x2105c0, 0x0},
+ {0x0106c0, 0x0},
+ {0x1106c0, 0x0},
+ {0x2106c0, 0x0},
+ {0x0107c0, 0x0},
+ {0x1107c0, 0x0},
+ {0x2107c0, 0x0},
+ {0x0108c0, 0x0},
+ {0x1108c0, 0x0},
+ {0x2108c0, 0x0},
+ {0x0100c1, 0x0},
+ {0x1100c1, 0x0},
+ {0x2100c1, 0x0},
+ {0x0101c1, 0x0},
+ {0x1101c1, 0x0},
+ {0x2101c1, 0x0},
+ {0x0102c1, 0x0},
+ {0x1102c1, 0x0},
+ {0x2102c1, 0x0},
+ {0x0103c1, 0x0},
+ {0x1103c1, 0x0},
+ {0x2103c1, 0x0},
+ {0x0104c1, 0x0},
+ {0x1104c1, 0x0},
+ {0x2104c1, 0x0},
+ {0x0105c1, 0x0},
+ {0x1105c1, 0x0},
+ {0x2105c1, 0x0},
+ {0x0106c1, 0x0},
+ {0x1106c1, 0x0},
+ {0x2106c1, 0x0},
+ {0x0107c1, 0x0},
+ {0x1107c1, 0x0},
+ {0x2107c1, 0x0},
+ {0x0108c1, 0x0},
+ {0x1108c1, 0x0},
+ {0x2108c1, 0x0},
+ {0x0100c2, 0x0},
+ {0x1100c2, 0x0},
+ {0x2100c2, 0x0},
+ {0x0101c2, 0x0},
+ {0x1101c2, 0x0},
+ {0x2101c2, 0x0},
+ {0x0102c2, 0x0},
+ {0x1102c2, 0x0},
+ {0x2102c2, 0x0},
+ {0x0103c2, 0x0},
+ {0x1103c2, 0x0},
+ {0x2103c2, 0x0},
+ {0x0104c2, 0x0},
+ {0x1104c2, 0x0},
+ {0x2104c2, 0x0},
+ {0x0105c2, 0x0},
+ {0x1105c2, 0x0},
+ {0x2105c2, 0x0},
+ {0x0106c2, 0x0},
+ {0x1106c2, 0x0},
+ {0x2106c2, 0x0},
+ {0x0107c2, 0x0},
+ {0x1107c2, 0x0},
+ {0x2107c2, 0x0},
+ {0x0108c2, 0x0},
+ {0x1108c2, 0x0},
+ {0x2108c2, 0x0},
+ {0x0100c3, 0x0},
+ {0x1100c3, 0x0},
+ {0x2100c3, 0x0},
+ {0x0101c3, 0x0},
+ {0x1101c3, 0x0},
+ {0x2101c3, 0x0},
+ {0x0102c3, 0x0},
+ {0x1102c3, 0x0},
+ {0x2102c3, 0x0},
+ {0x0103c3, 0x0},
+ {0x1103c3, 0x0},
+ {0x2103c3, 0x0},
+ {0x0104c3, 0x0},
+ {0x1104c3, 0x0},
+ {0x2104c3, 0x0},
+ {0x0105c3, 0x0},
+ {0x1105c3, 0x0},
+ {0x2105c3, 0x0},
+ {0x0106c3, 0x0},
+ {0x1106c3, 0x0},
+ {0x2106c3, 0x0},
+ {0x0107c3, 0x0},
+ {0x1107c3, 0x0},
+ {0x2107c3, 0x0},
+ {0x0108c3, 0x0},
+ {0x1108c3, 0x0},
+ {0x2108c3, 0x0},
+ {0x0110c0, 0x0},
+ {0x1110c0, 0x0},
+ {0x2110c0, 0x0},
+ {0x0111c0, 0x0},
+ {0x1111c0, 0x0},
+ {0x2111c0, 0x0},
+ {0x0112c0, 0x0},
+ {0x1112c0, 0x0},
+ {0x2112c0, 0x0},
+ {0x0113c0, 0x0},
+ {0x1113c0, 0x0},
+ {0x2113c0, 0x0},
+ {0x0114c0, 0x0},
+ {0x1114c0, 0x0},
+ {0x2114c0, 0x0},
+ {0x0115c0, 0x0},
+ {0x1115c0, 0x0},
+ {0x2115c0, 0x0},
+ {0x0116c0, 0x0},
+ {0x1116c0, 0x0},
+ {0x2116c0, 0x0},
+ {0x0117c0, 0x0},
+ {0x1117c0, 0x0},
+ {0x2117c0, 0x0},
+ {0x0118c0, 0x0},
+ {0x1118c0, 0x0},
+ {0x2118c0, 0x0},
+ {0x0110c1, 0x0},
+ {0x1110c1, 0x0},
+ {0x2110c1, 0x0},
+ {0x0111c1, 0x0},
+ {0x1111c1, 0x0},
+ {0x2111c1, 0x0},
+ {0x0112c1, 0x0},
+ {0x1112c1, 0x0},
+ {0x2112c1, 0x0},
+ {0x0113c1, 0x0},
+ {0x1113c1, 0x0},
+ {0x2113c1, 0x0},
+ {0x0114c1, 0x0},
+ {0x1114c1, 0x0},
+ {0x2114c1, 0x0},
+ {0x0115c1, 0x0},
+ {0x1115c1, 0x0},
+ {0x2115c1, 0x0},
+ {0x0116c1, 0x0},
+ {0x1116c1, 0x0},
+ {0x2116c1, 0x0},
+ {0x0117c1, 0x0},
+ {0x1117c1, 0x0},
+ {0x2117c1, 0x0},
+ {0x0118c1, 0x0},
+ {0x1118c1, 0x0},
+ {0x2118c1, 0x0},
+ {0x0110c2, 0x0},
+ {0x1110c2, 0x0},
+ {0x2110c2, 0x0},
+ {0x0111c2, 0x0},
+ {0x1111c2, 0x0},
+ {0x2111c2, 0x0},
+ {0x0112c2, 0x0},
+ {0x1112c2, 0x0},
+ {0x2112c2, 0x0},
+ {0x0113c2, 0x0},
+ {0x1113c2, 0x0},
+ {0x2113c2, 0x0},
+ {0x0114c2, 0x0},
+ {0x1114c2, 0x0},
+ {0x2114c2, 0x0},
+ {0x0115c2, 0x0},
+ {0x1115c2, 0x0},
+ {0x2115c2, 0x0},
+ {0x0116c2, 0x0},
+ {0x1116c2, 0x0},
+ {0x2116c2, 0x0},
+ {0x0117c2, 0x0},
+ {0x1117c2, 0x0},
+ {0x2117c2, 0x0},
+ {0x0118c2, 0x0},
+ {0x1118c2, 0x0},
+ {0x2118c2, 0x0},
+ {0x0110c3, 0x0},
+ {0x1110c3, 0x0},
+ {0x2110c3, 0x0},
+ {0x0111c3, 0x0},
+ {0x1111c3, 0x0},
+ {0x2111c3, 0x0},
+ {0x0112c3, 0x0},
+ {0x1112c3, 0x0},
+ {0x2112c3, 0x0},
+ {0x0113c3, 0x0},
+ {0x1113c3, 0x0},
+ {0x2113c3, 0x0},
+ {0x0114c3, 0x0},
+ {0x1114c3, 0x0},
+ {0x2114c3, 0x0},
+ {0x0115c3, 0x0},
+ {0x1115c3, 0x0},
+ {0x2115c3, 0x0},
+ {0x0116c3, 0x0},
+ {0x1116c3, 0x0},
+ {0x2116c3, 0x0},
+ {0x0117c3, 0x0},
+ {0x1117c3, 0x0},
+ {0x2117c3, 0x0},
+ {0x0118c3, 0x0},
+ {0x1118c3, 0x0},
+ {0x2118c3, 0x0},
+ {0x010020, 0x0},
+ {0x110020, 0x0},
+ {0x210020, 0x0},
+ {0x011020, 0x0},
+ {0x111020, 0x0},
+ {0x211020, 0x0},
+ {0x02007d, 0x0},
+ {0x12007d, 0x0},
+ {0x22007d, 0x0},
+ {0x010040, 0x0},
+ {0x010140, 0x0},
+ {0x010240, 0x0},
+ {0x010340, 0x0},
+ {0x010440, 0x0},
+ {0x010540, 0x0},
+ {0x010640, 0x0},
+ {0x010740, 0x0},
+ {0x010840, 0x0},
+ {0x010030, 0x0},
+ {0x010130, 0x0},
+ {0x010230, 0x0},
+ {0x010330, 0x0},
+ {0x010430, 0x0},
+ {0x010530, 0x0},
+ {0x010630, 0x0},
+ {0x010730, 0x0},
+ {0x010830, 0x0},
+ {0x011040, 0x0},
+ {0x011140, 0x0},
+ {0x011240, 0x0},
+ {0x011340, 0x0},
+ {0x011440, 0x0},
+ {0x011540, 0x0},
+ {0x011640, 0x0},
+ {0x011740, 0x0},
+ {0x011840, 0x0},
+ {0x011030, 0x0},
+ {0x011130, 0x0},
+ {0x011230, 0x0},
+ {0x011330, 0x0},
+ {0x011430, 0x0},
+ {0x011530, 0x0},
+ {0x011630, 0x0},
+ {0x011730, 0x0},
+ {0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x960 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x31f },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x834 },
+ { 0x54030, 0x105 },
+ { 0x54031, 0x18 },
+ { 0x54032, 0x200 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x810 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x1 },
+ { 0x54003, 0x42a },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x21f },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x54012, 0x1 },
+ { 0x54030, 0x105 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x10 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x960 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x61 },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x5400e, 0x1f7f },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x834 },
+ { 0x54030, 0x105 },
+ { 0x54031, 0x18 },
+ { 0x54032, 0x200 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x810 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x2 },
+ { 0x90033, 0x10 },
+ { 0x90034, 0x139 },
+ { 0x90035, 0xb },
+ { 0x90036, 0x7c0 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0x44 },
+ { 0x90039, 0x633 },
+ { 0x9003a, 0x159 },
+ { 0x9003b, 0x14f },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x47 },
+ { 0x9003f, 0x633 },
+ { 0x90040, 0x149 },
+ { 0x90041, 0x4f },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x179 },
+ { 0x90044, 0x8 },
+ { 0x90045, 0xe0 },
+ { 0x90046, 0x109 },
+ { 0x90047, 0x0 },
+ { 0x90048, 0x7c8 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x1 },
+ { 0x9004c, 0x8 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x45a },
+ { 0x9004f, 0x9 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x448 },
+ { 0x90052, 0x109 },
+ { 0x90053, 0x40 },
+ { 0x90054, 0x633 },
+ { 0x90055, 0x179 },
+ { 0x90056, 0x1 },
+ { 0x90057, 0x618 },
+ { 0x90058, 0x109 },
+ { 0x90059, 0x40c0 },
+ { 0x9005a, 0x633 },
+ { 0x9005b, 0x149 },
+ { 0x9005c, 0x8 },
+ { 0x9005d, 0x4 },
+ { 0x9005e, 0x48 },
+ { 0x9005f, 0x4040 },
+ { 0x90060, 0x633 },
+ { 0x90061, 0x149 },
+ { 0x90062, 0x0 },
+ { 0x90063, 0x4 },
+ { 0x90064, 0x48 },
+ { 0x90065, 0x40 },
+ { 0x90066, 0x633 },
+ { 0x90067, 0x149 },
+ { 0x90068, 0x10 },
+ { 0x90069, 0x4 },
+ { 0x9006a, 0x18 },
+ { 0x9006b, 0x0 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x78 },
+ { 0x9006e, 0x549 },
+ { 0x9006f, 0x633 },
+ { 0x90070, 0x159 },
+ { 0x90071, 0xd49 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0x94a },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x441 },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x149 },
+ { 0x9007a, 0x42 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x1 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x0 },
+ { 0x90081, 0xe0 },
+ { 0x90082, 0x109 },
+ { 0x90083, 0xa },
+ { 0x90084, 0x10 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0x9 },
+ { 0x90087, 0x3c0 },
+ { 0x90088, 0x149 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x159 },
+ { 0x9008c, 0x18 },
+ { 0x9008d, 0x10 },
+ { 0x9008e, 0x109 },
+ { 0x9008f, 0x0 },
+ { 0x90090, 0x3c0 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x18 },
+ { 0x90093, 0x4 },
+ { 0x90094, 0x48 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x58 },
+ { 0x90098, 0xb },
+ { 0x90099, 0x10 },
+ { 0x9009a, 0x109 },
+ { 0x9009b, 0x1 },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x5 },
+ { 0x9009f, 0x7c0 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x0 },
+ { 0x900a2, 0x8140 },
+ { 0x900a3, 0x10c },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x8138 },
+ { 0x900a6, 0x10c },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7c8 },
+ { 0x900a9, 0x101 },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x448 },
+ { 0x900ac, 0x109 },
+ { 0x900ad, 0xf },
+ { 0x900ae, 0x7c0 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x47 },
+ { 0x900b1, 0x630 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x8 },
+ { 0x900b4, 0x618 },
+ { 0x900b5, 0x109 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0xe0 },
+ { 0x900b8, 0x109 },
+ { 0x900b9, 0x0 },
+ { 0x900ba, 0x7c8 },
+ { 0x900bb, 0x109 },
+ { 0x900bc, 0x8 },
+ { 0x900bd, 0x8140 },
+ { 0x900be, 0x10c },
+ { 0x900bf, 0x0 },
+ { 0x900c0, 0x1 },
+ { 0x900c1, 0x8 },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x8 },
+ { 0x900c5, 0x8 },
+ { 0x900c6, 0x7c8 },
+ { 0x900c7, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x90026, 0x2b },
+ { 0x2000b, 0x4b },
+ { 0x2000c, 0x96 },
+ { 0x2000d, 0x5dc },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0x21 },
+ { 0x12000c, 0x42 },
+ { 0x12000d, 0x29a },
+ { 0x12000e, 0x21 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0xffff },
+ { 0x90013, 0x6152 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x0 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 2400mts 1D */
+ .drate = 2400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 1066mts 1D */
+ .drate = 1066,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P0 2400mts 2D */
+ .drate = 2400,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 2400, 1066, },
+};
+
diff --git a/board/freescale/imx8mm_ab2/ddr4_imx8mn_som_ld.c b/board/freescale/imx8mm_ab2/ddr4_imx8mn_som_ld.c
new file mode 100644
index 0000000000..a3577efd0b
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/ddr4_imx8mn_som_ld.c
@@ -0,0 +1,1056 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400000, 0x81040010 },
+ { 0x3d400030, 0x20 },
+ { 0x3d400034, 0x221306 },
+ { 0x3d400050, 0x210070 },
+ { 0x3d400054, 0x10008 },
+ { 0x3d400060, 0x0 },
+ { 0x3d400064, 0x6100dc },
+ { 0x3d4000c0, 0x0 },
+ { 0x3d4000c4, 0x1000 },
+ { 0x3d4000d0, 0xc00200c5 },
+ { 0x3d4000d4, 0x500000 },
+ { 0x3d4000dc, 0x2340105 },
+ { 0x3d4000e0, 0x0 },
+ { 0x3d4000e4, 0x110000 },
+ { 0x3d4000e8, 0x2000600 },
+ { 0x3d4000ec, 0x410 },
+ { 0x3d4000f0, 0x20 },
+ { 0x3d4000f4, 0xec7 },
+ { 0x3d400100, 0xd0c1b0d },
+ { 0x3d400104, 0x30313 },
+ { 0x3d400108, 0x508060a },
+ { 0x3d40010c, 0x400c },
+ { 0x3d400110, 0x6030306 },
+ { 0x3d400114, 0x4040302 },
+ { 0x3d40011c, 0x404 },
+ { 0x3d400120, 0x5050d08 },
+ { 0x3d400124, 0x20308 },
+ { 0x3d40012c, 0x1406010e },
+ { 0x3d400130, 0x8 },
+ { 0x3d40013c, 0x0 },
+ { 0x3d400180, 0x1000040 },
+ { 0x3d400184, 0x30d4 },
+ { 0x3d400190, 0x38b8204 },
+ { 0x3d400194, 0x2020303 },
+ { 0x3d400198, 0x7f04011 },
+ { 0x3d40019c, 0xb0 },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0x48005a },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x1 },
+ { 0x3d4001b4, 0xb04 },
+ { 0x3d4001b8, 0x4 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x0 },
+ { 0x3d400200, 0x3f1f },
+ { 0x3d400204, 0x3f0909 },
+ { 0x3d400208, 0x700 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf07 },
+ { 0x3d400220, 0x3f01 },
+ { 0x3d400240, 0x600061c },
+ { 0x3d400244, 0x1323 },
+ { 0x3d400400, 0x100 },
+ { 0x3d400250, 0x317d1a07 },
+ { 0x3d400254, 0xf },
+ { 0x3d40025c, 0x2a001b76 },
+ { 0x3d400264, 0x7300b473 },
+ { 0x3d40026c, 0x30000e06 },
+ { 0x3d400300, 0x14 },
+ { 0x3d40036c, 0x10 },
+ { 0x3d400404, 0x13193 },
+ { 0x3d400408, 0x6096 },
+ { 0x3d400490, 0x1 },
+ { 0x3d400494, 0x2000c00 },
+ { 0x3d400498, 0x3c00db },
+ { 0x3d40049c, 0x100009 },
+ { 0x3d4004a0, 0x2 },
+ { 0x3d402050, 0x210070 },
+ { 0x3d402064, 0x400093 },
+ { 0x3d4020dc, 0x40105 },
+ { 0x3d4020e0, 0x0 },
+ { 0x3d4020e8, 0x2000600 },
+ { 0x3d4020ec, 0x10 },
+ { 0x3d402100, 0xb081209 },
+ { 0x3d402104, 0x2020d },
+ { 0x3d402108, 0x5050309 },
+ { 0x3d40210c, 0x400c },
+ { 0x3d402110, 0x5030206 },
+ { 0x3d402114, 0x3030202 },
+ { 0x3d40211c, 0x303 },
+ { 0x3d402120, 0x4040d06 },
+ { 0x3d402124, 0x20208 },
+ { 0x3d40212c, 0x1205010e },
+ { 0x3d402130, 0x8 },
+ { 0x3d40213c, 0x0 },
+ { 0x3d402180, 0x1000040 },
+ { 0x3d402190, 0x3858204 },
+ { 0x3d402194, 0x2020303 },
+ { 0x3d4021b4, 0x504 },
+ { 0x3d4021b8, 0x4 },
+ { 0x3d402240, 0x6000604 },
+ { 0x3d4020f4, 0xec7 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x1005f, 0x2fd },
+ { 0x1015f, 0x2fd },
+ { 0x1105f, 0x2fd },
+ { 0x1115f, 0x2fd },
+ { 0x11005f, 0x2fd },
+ { 0x11015f, 0x2fd },
+ { 0x11105f, 0x2fd },
+ { 0x11115f, 0x2fd },
+ { 0x55, 0x355 },
+ { 0x1055, 0x355 },
+ { 0x2055, 0x355 },
+ { 0x3055, 0x355 },
+ { 0x4055, 0x55 },
+ { 0x5055, 0x55 },
+ { 0x6055, 0x355 },
+ { 0x7055, 0x355 },
+ { 0x8055, 0x355 },
+ { 0x9055, 0x355 },
+ { 0x200c5, 0xb },
+ { 0x1200c5, 0x6 },
+ { 0x2002e, 0x1 },
+ { 0x12002e, 0x1 },
+ { 0x20024, 0x8 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x8 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0xa },
+ { 0x120056, 0xa },
+ { 0x1004d, 0x1a },
+ { 0x1014d, 0x1a },
+ { 0x1104d, 0x1a },
+ { 0x1114d, 0x1a },
+ { 0x11004d, 0x1a },
+ { 0x11014d, 0x1a },
+ { 0x11104d, 0x1a },
+ { 0x11114d, 0x1a },
+ { 0x10049, 0xe38 },
+ { 0x10149, 0xe38 },
+ { 0x11049, 0xe38 },
+ { 0x11149, 0xe38 },
+ { 0x110049, 0xe38 },
+ { 0x110149, 0xe38 },
+ { 0x111049, 0xe38 },
+ { 0x111149, 0xe38 },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x1 },
+ { 0x20075, 0x2 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x190 },
+ { 0x120008, 0x10a },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x268 },
+ { 0x10043, 0x5b1 },
+ { 0x10143, 0x5b1 },
+ { 0x11043, 0x5b1 },
+ { 0x11143, 0x5b1 },
+ { 0x1200b2, 0x268 },
+ { 0x110043, 0x5b1 },
+ { 0x110143, 0x5b1 },
+ { 0x111043, 0x5b1 },
+ { 0x111143, 0x5b1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x20019, 0x5 },
+ { 0x120019, 0x5 },
+ { 0x200f0, 0x5555 },
+ { 0x200f1, 0x5555 },
+ { 0x200f2, 0x5555 },
+ { 0x200f3, 0x5555 },
+ { 0x200f4, 0x5555 },
+ { 0x200f5, 0x5555 },
+ { 0x200f6, 0x5555 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x2005b, 0x7529 },
+ { 0x2005c, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x200cc, 0x1f7 },
+ { 0x1200c7, 0x21 },
+ { 0x1200ca, 0x24 },
+ { 0x1200cc, 0x1f7 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x0200b2, 0x0},
+ {0x1200b2, 0x0},
+ {0x2200b2, 0x0},
+ {0x0200cb, 0x0},
+ {0x010043, 0x0},
+ {0x110043, 0x0},
+ {0x210043, 0x0},
+ {0x010143, 0x0},
+ {0x110143, 0x0},
+ {0x210143, 0x0},
+ {0x011043, 0x0},
+ {0x111043, 0x0},
+ {0x211043, 0x0},
+ {0x011143, 0x0},
+ {0x111143, 0x0},
+ {0x211143, 0x0},
+ {0x000080, 0x0},
+ {0x100080, 0x0},
+ {0x200080, 0x0},
+ {0x001080, 0x0},
+ {0x101080, 0x0},
+ {0x201080, 0x0},
+ {0x002080, 0x0},
+ {0x102080, 0x0},
+ {0x202080, 0x0},
+ {0x003080, 0x0},
+ {0x103080, 0x0},
+ {0x203080, 0x0},
+ {0x004080, 0x0},
+ {0x104080, 0x0},
+ {0x204080, 0x0},
+ {0x005080, 0x0},
+ {0x105080, 0x0},
+ {0x205080, 0x0},
+ {0x006080, 0x0},
+ {0x106080, 0x0},
+ {0x206080, 0x0},
+ {0x007080, 0x0},
+ {0x107080, 0x0},
+ {0x207080, 0x0},
+ {0x008080, 0x0},
+ {0x108080, 0x0},
+ {0x208080, 0x0},
+ {0x009080, 0x0},
+ {0x109080, 0x0},
+ {0x209080, 0x0},
+ {0x010080, 0x0},
+ {0x110080, 0x0},
+ {0x210080, 0x0},
+ {0x010180, 0x0},
+ {0x110180, 0x0},
+ {0x210180, 0x0},
+ {0x010081, 0x0},
+ {0x110081, 0x0},
+ {0x210081, 0x0},
+ {0x010181, 0x0},
+ {0x110181, 0x0},
+ {0x210181, 0x0},
+ {0x010082, 0x0},
+ {0x110082, 0x0},
+ {0x210082, 0x0},
+ {0x010182, 0x0},
+ {0x110182, 0x0},
+ {0x210182, 0x0},
+ {0x010083, 0x0},
+ {0x110083, 0x0},
+ {0x210083, 0x0},
+ {0x010183, 0x0},
+ {0x110183, 0x0},
+ {0x210183, 0x0},
+ {0x011080, 0x0},
+ {0x111080, 0x0},
+ {0x211080, 0x0},
+ {0x011180, 0x0},
+ {0x111180, 0x0},
+ {0x211180, 0x0},
+ {0x011081, 0x0},
+ {0x111081, 0x0},
+ {0x211081, 0x0},
+ {0x011181, 0x0},
+ {0x111181, 0x0},
+ {0x211181, 0x0},
+ {0x011082, 0x0},
+ {0x111082, 0x0},
+ {0x211082, 0x0},
+ {0x011182, 0x0},
+ {0x111182, 0x0},
+ {0x211182, 0x0},
+ {0x011083, 0x0},
+ {0x111083, 0x0},
+ {0x211083, 0x0},
+ {0x011183, 0x0},
+ {0x111183, 0x0},
+ {0x211183, 0x0},
+ {0x0100d0, 0x0},
+ {0x1100d0, 0x0},
+ {0x2100d0, 0x0},
+ {0x0101d0, 0x0},
+ {0x1101d0, 0x0},
+ {0x2101d0, 0x0},
+ {0x0100d1, 0x0},
+ {0x1100d1, 0x0},
+ {0x2100d1, 0x0},
+ {0x0101d1, 0x0},
+ {0x1101d1, 0x0},
+ {0x2101d1, 0x0},
+ {0x0100d2, 0x0},
+ {0x1100d2, 0x0},
+ {0x2100d2, 0x0},
+ {0x0101d2, 0x0},
+ {0x1101d2, 0x0},
+ {0x2101d2, 0x0},
+ {0x0100d3, 0x0},
+ {0x1100d3, 0x0},
+ {0x2100d3, 0x0},
+ {0x0101d3, 0x0},
+ {0x1101d3, 0x0},
+ {0x2101d3, 0x0},
+ {0x0110d0, 0x0},
+ {0x1110d0, 0x0},
+ {0x2110d0, 0x0},
+ {0x0111d0, 0x0},
+ {0x1111d0, 0x0},
+ {0x2111d0, 0x0},
+ {0x0110d1, 0x0},
+ {0x1110d1, 0x0},
+ {0x2110d1, 0x0},
+ {0x0111d1, 0x0},
+ {0x1111d1, 0x0},
+ {0x2111d1, 0x0},
+ {0x0110d2, 0x0},
+ {0x1110d2, 0x0},
+ {0x2110d2, 0x0},
+ {0x0111d2, 0x0},
+ {0x1111d2, 0x0},
+ {0x2111d2, 0x0},
+ {0x0110d3, 0x0},
+ {0x1110d3, 0x0},
+ {0x2110d3, 0x0},
+ {0x0111d3, 0x0},
+ {0x1111d3, 0x0},
+ {0x2111d3, 0x0},
+ {0x010068, 0x0},
+ {0x010168, 0x0},
+ {0x010268, 0x0},
+ {0x010368, 0x0},
+ {0x010468, 0x0},
+ {0x010568, 0x0},
+ {0x010668, 0x0},
+ {0x010768, 0x0},
+ {0x010868, 0x0},
+ {0x010069, 0x0},
+ {0x010169, 0x0},
+ {0x010269, 0x0},
+ {0x010369, 0x0},
+ {0x010469, 0x0},
+ {0x010569, 0x0},
+ {0x010669, 0x0},
+ {0x010769, 0x0},
+ {0x010869, 0x0},
+ {0x01006a, 0x0},
+ {0x01016a, 0x0},
+ {0x01026a, 0x0},
+ {0x01036a, 0x0},
+ {0x01046a, 0x0},
+ {0x01056a, 0x0},
+ {0x01066a, 0x0},
+ {0x01076a, 0x0},
+ {0x01086a, 0x0},
+ {0x01006b, 0x0},
+ {0x01016b, 0x0},
+ {0x01026b, 0x0},
+ {0x01036b, 0x0},
+ {0x01046b, 0x0},
+ {0x01056b, 0x0},
+ {0x01066b, 0x0},
+ {0x01076b, 0x0},
+ {0x01086b, 0x0},
+ {0x011068, 0x0},
+ {0x011168, 0x0},
+ {0x011268, 0x0},
+ {0x011368, 0x0},
+ {0x011468, 0x0},
+ {0x011568, 0x0},
+ {0x011668, 0x0},
+ {0x011768, 0x0},
+ {0x011868, 0x0},
+ {0x011069, 0x0},
+ {0x011169, 0x0},
+ {0x011269, 0x0},
+ {0x011369, 0x0},
+ {0x011469, 0x0},
+ {0x011569, 0x0},
+ {0x011669, 0x0},
+ {0x011769, 0x0},
+ {0x011869, 0x0},
+ {0x01106a, 0x0},
+ {0x01116a, 0x0},
+ {0x01126a, 0x0},
+ {0x01136a, 0x0},
+ {0x01146a, 0x0},
+ {0x01156a, 0x0},
+ {0x01166a, 0x0},
+ {0x01176a, 0x0},
+ {0x01186a, 0x0},
+ {0x01106b, 0x0},
+ {0x01116b, 0x0},
+ {0x01126b, 0x0},
+ {0x01136b, 0x0},
+ {0x01146b, 0x0},
+ {0x01156b, 0x0},
+ {0x01166b, 0x0},
+ {0x01176b, 0x0},
+ {0x01186b, 0x0},
+ {0x01008c, 0x0},
+ {0x11008c, 0x0},
+ {0x21008c, 0x0},
+ {0x01018c, 0x0},
+ {0x11018c, 0x0},
+ {0x21018c, 0x0},
+ {0x01008d, 0x0},
+ {0x11008d, 0x0},
+ {0x21008d, 0x0},
+ {0x01018d, 0x0},
+ {0x11018d, 0x0},
+ {0x21018d, 0x0},
+ {0x01008e, 0x0},
+ {0x11008e, 0x0},
+ {0x21008e, 0x0},
+ {0x01018e, 0x0},
+ {0x11018e, 0x0},
+ {0x21018e, 0x0},
+ {0x01008f, 0x0},
+ {0x11008f, 0x0},
+ {0x21008f, 0x0},
+ {0x01018f, 0x0},
+ {0x11018f, 0x0},
+ {0x21018f, 0x0},
+ {0x01108c, 0x0},
+ {0x11108c, 0x0},
+ {0x21108c, 0x0},
+ {0x01118c, 0x0},
+ {0x11118c, 0x0},
+ {0x21118c, 0x0},
+ {0x01108d, 0x0},
+ {0x11108d, 0x0},
+ {0x21108d, 0x0},
+ {0x01118d, 0x0},
+ {0x11118d, 0x0},
+ {0x21118d, 0x0},
+ {0x01108e, 0x0},
+ {0x11108e, 0x0},
+ {0x21108e, 0x0},
+ {0x01118e, 0x0},
+ {0x11118e, 0x0},
+ {0x21118e, 0x0},
+ {0x01108f, 0x0},
+ {0x11108f, 0x0},
+ {0x21108f, 0x0},
+ {0x01118f, 0x0},
+ {0x11118f, 0x0},
+ {0x21118f, 0x0},
+ {0x0100c0, 0x0},
+ {0x1100c0, 0x0},
+ {0x2100c0, 0x0},
+ {0x0101c0, 0x0},
+ {0x1101c0, 0x0},
+ {0x2101c0, 0x0},
+ {0x0102c0, 0x0},
+ {0x1102c0, 0x0},
+ {0x2102c0, 0x0},
+ {0x0103c0, 0x0},
+ {0x1103c0, 0x0},
+ {0x2103c0, 0x0},
+ {0x0104c0, 0x0},
+ {0x1104c0, 0x0},
+ {0x2104c0, 0x0},
+ {0x0105c0, 0x0},
+ {0x1105c0, 0x0},
+ {0x2105c0, 0x0},
+ {0x0106c0, 0x0},
+ {0x1106c0, 0x0},
+ {0x2106c0, 0x0},
+ {0x0107c0, 0x0},
+ {0x1107c0, 0x0},
+ {0x2107c0, 0x0},
+ {0x0108c0, 0x0},
+ {0x1108c0, 0x0},
+ {0x2108c0, 0x0},
+ {0x0100c1, 0x0},
+ {0x1100c1, 0x0},
+ {0x2100c1, 0x0},
+ {0x0101c1, 0x0},
+ {0x1101c1, 0x0},
+ {0x2101c1, 0x0},
+ {0x0102c1, 0x0},
+ {0x1102c1, 0x0},
+ {0x2102c1, 0x0},
+ {0x0103c1, 0x0},
+ {0x1103c1, 0x0},
+ {0x2103c1, 0x0},
+ {0x0104c1, 0x0},
+ {0x1104c1, 0x0},
+ {0x2104c1, 0x0},
+ {0x0105c1, 0x0},
+ {0x1105c1, 0x0},
+ {0x2105c1, 0x0},
+ {0x0106c1, 0x0},
+ {0x1106c1, 0x0},
+ {0x2106c1, 0x0},
+ {0x0107c1, 0x0},
+ {0x1107c1, 0x0},
+ {0x2107c1, 0x0},
+ {0x0108c1, 0x0},
+ {0x1108c1, 0x0},
+ {0x2108c1, 0x0},
+ {0x0100c2, 0x0},
+ {0x1100c2, 0x0},
+ {0x2100c2, 0x0},
+ {0x0101c2, 0x0},
+ {0x1101c2, 0x0},
+ {0x2101c2, 0x0},
+ {0x0102c2, 0x0},
+ {0x1102c2, 0x0},
+ {0x2102c2, 0x0},
+ {0x0103c2, 0x0},
+ {0x1103c2, 0x0},
+ {0x2103c2, 0x0},
+ {0x0104c2, 0x0},
+ {0x1104c2, 0x0},
+ {0x2104c2, 0x0},
+ {0x0105c2, 0x0},
+ {0x1105c2, 0x0},
+ {0x2105c2, 0x0},
+ {0x0106c2, 0x0},
+ {0x1106c2, 0x0},
+ {0x2106c2, 0x0},
+ {0x0107c2, 0x0},
+ {0x1107c2, 0x0},
+ {0x2107c2, 0x0},
+ {0x0108c2, 0x0},
+ {0x1108c2, 0x0},
+ {0x2108c2, 0x0},
+ {0x0100c3, 0x0},
+ {0x1100c3, 0x0},
+ {0x2100c3, 0x0},
+ {0x0101c3, 0x0},
+ {0x1101c3, 0x0},
+ {0x2101c3, 0x0},
+ {0x0102c3, 0x0},
+ {0x1102c3, 0x0},
+ {0x2102c3, 0x0},
+ {0x0103c3, 0x0},
+ {0x1103c3, 0x0},
+ {0x2103c3, 0x0},
+ {0x0104c3, 0x0},
+ {0x1104c3, 0x0},
+ {0x2104c3, 0x0},
+ {0x0105c3, 0x0},
+ {0x1105c3, 0x0},
+ {0x2105c3, 0x0},
+ {0x0106c3, 0x0},
+ {0x1106c3, 0x0},
+ {0x2106c3, 0x0},
+ {0x0107c3, 0x0},
+ {0x1107c3, 0x0},
+ {0x2107c3, 0x0},
+ {0x0108c3, 0x0},
+ {0x1108c3, 0x0},
+ {0x2108c3, 0x0},
+ {0x0110c0, 0x0},
+ {0x1110c0, 0x0},
+ {0x2110c0, 0x0},
+ {0x0111c0, 0x0},
+ {0x1111c0, 0x0},
+ {0x2111c0, 0x0},
+ {0x0112c0, 0x0},
+ {0x1112c0, 0x0},
+ {0x2112c0, 0x0},
+ {0x0113c0, 0x0},
+ {0x1113c0, 0x0},
+ {0x2113c0, 0x0},
+ {0x0114c0, 0x0},
+ {0x1114c0, 0x0},
+ {0x2114c0, 0x0},
+ {0x0115c0, 0x0},
+ {0x1115c0, 0x0},
+ {0x2115c0, 0x0},
+ {0x0116c0, 0x0},
+ {0x1116c0, 0x0},
+ {0x2116c0, 0x0},
+ {0x0117c0, 0x0},
+ {0x1117c0, 0x0},
+ {0x2117c0, 0x0},
+ {0x0118c0, 0x0},
+ {0x1118c0, 0x0},
+ {0x2118c0, 0x0},
+ {0x0110c1, 0x0},
+ {0x1110c1, 0x0},
+ {0x2110c1, 0x0},
+ {0x0111c1, 0x0},
+ {0x1111c1, 0x0},
+ {0x2111c1, 0x0},
+ {0x0112c1, 0x0},
+ {0x1112c1, 0x0},
+ {0x2112c1, 0x0},
+ {0x0113c1, 0x0},
+ {0x1113c1, 0x0},
+ {0x2113c1, 0x0},
+ {0x0114c1, 0x0},
+ {0x1114c1, 0x0},
+ {0x2114c1, 0x0},
+ {0x0115c1, 0x0},
+ {0x1115c1, 0x0},
+ {0x2115c1, 0x0},
+ {0x0116c1, 0x0},
+ {0x1116c1, 0x0},
+ {0x2116c1, 0x0},
+ {0x0117c1, 0x0},
+ {0x1117c1, 0x0},
+ {0x2117c1, 0x0},
+ {0x0118c1, 0x0},
+ {0x1118c1, 0x0},
+ {0x2118c1, 0x0},
+ {0x0110c2, 0x0},
+ {0x1110c2, 0x0},
+ {0x2110c2, 0x0},
+ {0x0111c2, 0x0},
+ {0x1111c2, 0x0},
+ {0x2111c2, 0x0},
+ {0x0112c2, 0x0},
+ {0x1112c2, 0x0},
+ {0x2112c2, 0x0},
+ {0x0113c2, 0x0},
+ {0x1113c2, 0x0},
+ {0x2113c2, 0x0},
+ {0x0114c2, 0x0},
+ {0x1114c2, 0x0},
+ {0x2114c2, 0x0},
+ {0x0115c2, 0x0},
+ {0x1115c2, 0x0},
+ {0x2115c2, 0x0},
+ {0x0116c2, 0x0},
+ {0x1116c2, 0x0},
+ {0x2116c2, 0x0},
+ {0x0117c2, 0x0},
+ {0x1117c2, 0x0},
+ {0x2117c2, 0x0},
+ {0x0118c2, 0x0},
+ {0x1118c2, 0x0},
+ {0x2118c2, 0x0},
+ {0x0110c3, 0x0},
+ {0x1110c3, 0x0},
+ {0x2110c3, 0x0},
+ {0x0111c3, 0x0},
+ {0x1111c3, 0x0},
+ {0x2111c3, 0x0},
+ {0x0112c3, 0x0},
+ {0x1112c3, 0x0},
+ {0x2112c3, 0x0},
+ {0x0113c3, 0x0},
+ {0x1113c3, 0x0},
+ {0x2113c3, 0x0},
+ {0x0114c3, 0x0},
+ {0x1114c3, 0x0},
+ {0x2114c3, 0x0},
+ {0x0115c3, 0x0},
+ {0x1115c3, 0x0},
+ {0x2115c3, 0x0},
+ {0x0116c3, 0x0},
+ {0x1116c3, 0x0},
+ {0x2116c3, 0x0},
+ {0x0117c3, 0x0},
+ {0x1117c3, 0x0},
+ {0x2117c3, 0x0},
+ {0x0118c3, 0x0},
+ {0x1118c3, 0x0},
+ {0x2118c3, 0x0},
+ {0x010020, 0x0},
+ {0x110020, 0x0},
+ {0x210020, 0x0},
+ {0x011020, 0x0},
+ {0x111020, 0x0},
+ {0x211020, 0x0},
+ {0x02007d, 0x0},
+ {0x12007d, 0x0},
+ {0x22007d, 0x0},
+ {0x010040, 0x0},
+ {0x010140, 0x0},
+ {0x010240, 0x0},
+ {0x010340, 0x0},
+ {0x010440, 0x0},
+ {0x010540, 0x0},
+ {0x010640, 0x0},
+ {0x010740, 0x0},
+ {0x010840, 0x0},
+ {0x010030, 0x0},
+ {0x010130, 0x0},
+ {0x010230, 0x0},
+ {0x010330, 0x0},
+ {0x010430, 0x0},
+ {0x010530, 0x0},
+ {0x010630, 0x0},
+ {0x010730, 0x0},
+ {0x010830, 0x0},
+ {0x011040, 0x0},
+ {0x011140, 0x0},
+ {0x011240, 0x0},
+ {0x011340, 0x0},
+ {0x011440, 0x0},
+ {0x011540, 0x0},
+ {0x011640, 0x0},
+ {0x011740, 0x0},
+ {0x011840, 0x0},
+ {0x011030, 0x0},
+ {0x011130, 0x0},
+ {0x011230, 0x0},
+ {0x011330, 0x0},
+ {0x011430, 0x0},
+ {0x011530, 0x0},
+ {0x011630, 0x0},
+ {0x011730, 0x0},
+ {0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x640 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x31f },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x234 },
+ { 0x54030, 0x105 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x410 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x1 },
+ { 0x54003, 0x42a },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x21f },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x4 },
+ { 0x54030, 0x105 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x10 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x640 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x61 },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x5400e, 0x1f7f },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x234 },
+ { 0x54030, 0x105 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x410 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x2 },
+ { 0x90033, 0x10 },
+ { 0x90034, 0x139 },
+ { 0x90035, 0xb },
+ { 0x90036, 0x7c0 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0x44 },
+ { 0x90039, 0x633 },
+ { 0x9003a, 0x159 },
+ { 0x9003b, 0x14f },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x47 },
+ { 0x9003f, 0x633 },
+ { 0x90040, 0x149 },
+ { 0x90041, 0x4f },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x179 },
+ { 0x90044, 0x8 },
+ { 0x90045, 0xe0 },
+ { 0x90046, 0x109 },
+ { 0x90047, 0x0 },
+ { 0x90048, 0x7c8 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x1 },
+ { 0x9004c, 0x8 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x45a },
+ { 0x9004f, 0x9 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x448 },
+ { 0x90052, 0x109 },
+ { 0x90053, 0x40 },
+ { 0x90054, 0x633 },
+ { 0x90055, 0x179 },
+ { 0x90056, 0x1 },
+ { 0x90057, 0x618 },
+ { 0x90058, 0x109 },
+ { 0x90059, 0x40c0 },
+ { 0x9005a, 0x633 },
+ { 0x9005b, 0x149 },
+ { 0x9005c, 0x8 },
+ { 0x9005d, 0x4 },
+ { 0x9005e, 0x48 },
+ { 0x9005f, 0x4040 },
+ { 0x90060, 0x633 },
+ { 0x90061, 0x149 },
+ { 0x90062, 0x0 },
+ { 0x90063, 0x4 },
+ { 0x90064, 0x48 },
+ { 0x90065, 0x40 },
+ { 0x90066, 0x633 },
+ { 0x90067, 0x149 },
+ { 0x90068, 0x10 },
+ { 0x90069, 0x4 },
+ { 0x9006a, 0x18 },
+ { 0x9006b, 0x0 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x78 },
+ { 0x9006e, 0x549 },
+ { 0x9006f, 0x633 },
+ { 0x90070, 0x159 },
+ { 0x90071, 0xd49 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0x94a },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x441 },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x149 },
+ { 0x9007a, 0x42 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x1 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x0 },
+ { 0x90081, 0xe0 },
+ { 0x90082, 0x109 },
+ { 0x90083, 0xa },
+ { 0x90084, 0x10 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0x9 },
+ { 0x90087, 0x3c0 },
+ { 0x90088, 0x149 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x159 },
+ { 0x9008c, 0x18 },
+ { 0x9008d, 0x10 },
+ { 0x9008e, 0x109 },
+ { 0x9008f, 0x0 },
+ { 0x90090, 0x3c0 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x18 },
+ { 0x90093, 0x4 },
+ { 0x90094, 0x48 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x58 },
+ { 0x90098, 0xb },
+ { 0x90099, 0x10 },
+ { 0x9009a, 0x109 },
+ { 0x9009b, 0x1 },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x5 },
+ { 0x9009f, 0x7c0 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x0 },
+ { 0x900a2, 0x8140 },
+ { 0x900a3, 0x10c },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x8138 },
+ { 0x900a6, 0x10c },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7c8 },
+ { 0x900a9, 0x101 },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x448 },
+ { 0x900ac, 0x109 },
+ { 0x900ad, 0xf },
+ { 0x900ae, 0x7c0 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x47 },
+ { 0x900b1, 0x630 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x8 },
+ { 0x900b4, 0x618 },
+ { 0x900b5, 0x109 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0xe0 },
+ { 0x900b8, 0x109 },
+ { 0x900b9, 0x0 },
+ { 0x900ba, 0x7c8 },
+ { 0x900bb, 0x109 },
+ { 0x900bc, 0x8 },
+ { 0x900bd, 0x8140 },
+ { 0x900be, 0x10c },
+ { 0x900bf, 0x0 },
+ { 0x900c0, 0x1 },
+ { 0x900c1, 0x8 },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x8 },
+ { 0x900c5, 0x8 },
+ { 0x900c6, 0x7c8 },
+ { 0x900c7, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x90026, 0x2b },
+ { 0x2000b, 0x32 },
+ { 0x2000c, 0x64 },
+ { 0x2000d, 0x3e8 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0x21 },
+ { 0x12000c, 0x42 },
+ { 0x12000d, 0x29a },
+ { 0x12000e, 0x21 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0xffff },
+ { 0x90013, 0x6152 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x0 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 1600mts 1D */
+ .drate = 1600,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 1066mts 1D */
+ .drate = 1066,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P0 1600mts 2D */
+ .drate = 1600,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 1600, 1066, },
+};
diff --git a/board/freescale/imx8mm_ab2/imx8mm_ab2.c b/board/freescale/imx8mm_ab2/imx8mm_ab2.c
new file mode 100644
index 0000000000..e788bff3e1
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/imx8mm_ab2.c
@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <power/regulator.h>
+#if defined(CONFIG_IMX8MM)
+#include <asm/arch/imx8mm_pins.h>
+#else
+#include <asm/arch/imx8mn_pins.h>
+#endif
+#include <asm/global_data.h>
+#include <asm/arch/sys_proto.h>
+#include <asm-generic/gpio.h>
+#include <asm/mach-imx/dma.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <spl.h>
+#include <usb.h>
+#include "../common/tcpc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PWR_EN_5V0 IMX_GPIO_NR(1, 7)
+#define PWR_EN_ANA IMX_GPIO_NR(1, 10)
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+#if defined(CONFIG_IMX8MM)
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pwr_en_5v0[] = {
+ IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pwr_en_ana[] = {
+ IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#endif
+
+#if defined(CONFIG_IMX8MN)
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pwr_en_5v0[] = {
+ IMX8MN_PAD_GPIO1_IO07__GPIO1_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pwr_en_ana[] = {
+ IMX8MN_PAD_GPIO1_IO10__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#endif
+
+#ifdef CONFIG_NAND_MXS
+static void setup_gpmi_nand(void)
+{
+ init_nand_clk();
+}
+#endif
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ init_uart_clk(1);
+
+ imx_iomux_v3_setup_multiple_pads(pwr_en_5v0, ARRAY_SIZE(pwr_en_5v0));
+ gpio_request(PWR_EN_5V0, "pwr_en_5v0");
+ gpio_direction_output(PWR_EN_5V0, 1);
+
+ imx_iomux_v3_setup_multiple_pads(pwr_en_ana, ARRAY_SIZE(pwr_en_ana));
+ gpio_request(PWR_EN_ANA, "pwr_en_ana");
+ gpio_direction_output(PWR_EN_ANA, 0);
+
+ return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0);
+
+ return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_TCPC
+struct tcpc_port port1;
+
+struct tcpc_port_config port1_config = {
+ .i2c_bus = 1, /* i2c2*/
+ .addr = 0x1d,
+ .port_type = TYPEC_PORT_UFP,
+ .max_snk_mv = 5000,
+ .max_snk_ma = 3000,
+ .max_snk_mw = 15000,
+ .op_snk_mv = 9000,
+};
+
+static int setup_typec(void)
+{
+ int ret;
+
+ ret = tcpc_init(&port1, port1_config, NULL);
+ if (ret) {
+ printf("%s: tcpc port1 init failed, err=%d\n", __func__, ret);
+ }
+
+ return ret;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int ret = 0;
+
+ imx8m_usb_power(index, true);
+
+ if (init == USB_INIT_HOST)
+ tcpc_setup_dfp_mode(&port1);
+ else
+ tcpc_setup_ufp_mode(&port1);
+
+ return ret;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ int ret = 0;
+
+ if (init == USB_INIT_HOST)
+ ret = tcpc_disable_src_vbus(&port1);
+
+ imx8m_usb_power(index, false);
+
+ return ret;
+}
+
+int board_ehci_usb_phy_mode(struct udevice *dev)
+{
+ enum typec_cc_polarity pol;
+ enum typec_cc_state state;
+ int ret = 0;
+
+ tcpc_setup_ufp_mode(&port1);
+ ret = tcpc_get_cc_status(&port1, &pol, &state);
+ if (!ret) {
+ if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD)
+ return USB_INIT_HOST;
+ }
+
+ return USB_INIT_DEVICE;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_DM_REGULATOR
+ regulators_enable_boot_on(false);
+#endif
+
+#ifdef CONFIG_USB_TCPC
+ setup_typec();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_nand();
+#endif
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
+ board_late_mmc_env_init();
+
+ if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
+ env_set("board_name", "AB2");
+
+ if (IS_ENABLED(CONFIG_IMX8MM))
+ env_set("board_rev", "iMX8MM");
+ else {
+ env_set("board_rev", "iMX8MN");
+ env_set("board", "imx8mn_ab2");
+ }
+
+ return 0;
+}
diff --git a/board/freescale/imx8mm_ab2/imximage-8mm-fspi.cfg b/board/freescale/imx8mm_ab2/imximage-8mm-fspi.cfg
new file mode 100644
index 0000000000..fcace8a93a
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/imximage-8mm-fspi.cfg
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+BOOT_FROM fspi
+LOADER u-boot-spl-ddr.bin 0x7E2000
diff --git a/board/freescale/imx8mm_ab2/imximage-8mm.cfg b/board/freescale/imx8mm_ab2/imximage-8mm.cfg
new file mode 100644
index 0000000000..20061521f2
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/imximage-8mm.cfg
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+
+BOOT_FROM sd
+LOADER u-boot-spl-ddr.bin 0x7E1000
diff --git a/board/freescale/imx8mm_ab2/imximage-8mn.cfg b/board/freescale/imx8mm_ab2/imximage-8mn.cfg
new file mode 100644
index 0000000000..0edda9c5e0
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/imximage-8mn.cfg
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+
+ROM_VERSION v2
+BOOT_FROM sd
+LOADER u-boot-spl-ddr.bin 0x912000
diff --git a/board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c b/board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c
new file mode 100644
index 0000000000..664c08e718
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c
@@ -0,0 +1,1855 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /* Initialize DDRC registers */
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x223 },
+ { 0x3d400024, 0x16e3600 },
+ { 0x3d400064, 0x5b00d2 },
+ { 0x3d4000d0, 0xc00305ba },
+ { 0x3d4000d4, 0x940000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x191e1920 },
+ { 0x3d400104, 0x60630 },
+ { 0x3d40010c, 0xb0b000 },
+ { 0x3d400110, 0xe04080e },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0xd8 },
+ { 0x3d400144, 0x96004b },
+ { 0x3d400180, 0x2ee0017 },
+ { 0x3d400184, 0x2605b8e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x0 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x1f },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+
+ /* performance setting */
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+
+ /* P1: 400mts */
+ { 0x3d402020, 0x21 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+
+ /* p2: 100mts */
+ { 0x3d403020, 0x21 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+
+ /* default boot point */
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x220024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0xa },
+ { 0x220056, 0xa },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x2ee },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x1200c7, 0x21 },
+ { 0x2200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x1200ca, 0x24 },
+ { 0x2200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
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+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xf },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x630 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x630 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x630 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x630 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x630 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x630 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x630 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x630 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x630 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x630 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x630 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x630 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xa },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x2 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x10 },
+ { 0x900a6, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x623 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x623 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a7, 0x0 },
+ { 0x900a8, 0x790 },
+ { 0x900a9, 0x11a },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x7aa },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x10 },
+ { 0x900ae, 0x7b2 },
+ { 0x900af, 0x2a },
+ { 0x900b0, 0x0 },
+ { 0x900b1, 0x7c8 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },