diff options
Diffstat (limited to 'board/MAI/bios_emulator/scitech/src/biosemu')
-rw-r--r-- | board/MAI/bios_emulator/scitech/src/biosemu/besys.c | 280 | ||||
-rw-r--r-- | board/MAI/bios_emulator/scitech/src/biosemu/bios.c | 204 | ||||
-rw-r--r-- | board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c | 66 | ||||
-rw-r--r-- | board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c | 610 |
4 files changed, 580 insertions, 580 deletions
diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/besys.c b/board/MAI/bios_emulator/scitech/src/biosemu/besys.c index 7f7ea999393..1512ce9bf9d 100644 --- a/board/MAI/bios_emulator/scitech/src/biosemu/besys.c +++ b/board/MAI/bios_emulator/scitech/src/biosemu/besys.c @@ -77,20 +77,20 @@ u8 X86API BE_rdb( u8 val = 0; if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { - val = *(u8*)(_BE_env.biosmem_base + addr - 0xC0000); - } + val = *(u8*)(_BE_env.biosmem_base + addr - 0xC0000); + } else if (addr >= 0xA0000 && addr <= 0xFFFFF) { - val = readb(_BE_env.busmem_base, addr - 0xA0000); - } + val = readb(_BE_env.busmem_base, addr - 0xA0000); + } else if (addr > M.mem_size - 1) { DB( printk("mem_read: address %#lx out of range!\n", addr);) - HALT_SYS(); - } + HALT_SYS(); + } else { - val = *(u8*)(M.mem_base + addr); - } + val = *(u8*)(M.mem_base + addr); + } DB( if (DEBUG_MEM()) - printk("%#08x 1 -> %#x\n", addr, val);) + printk("%#08x 1 -> %#x\n", addr, val);) return val; } @@ -112,42 +112,42 @@ u16 X86API BE_rdw( if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { #ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - addr -= 0xC0000; - val = ( *(u8*)(_BE_env.biosmem_base + addr) | - (*(u8*)(_BE_env.biosmem_base + addr + 1) << 8)); - } - else + if (addr & 0x1) { + addr -= 0xC0000; + val = ( *(u8*)(_BE_env.biosmem_base + addr) | + (*(u8*)(_BE_env.biosmem_base + addr + 1) << 8)); + } + else #endif - val = *(u16*)(_BE_env.biosmem_base + addr - 0xC0000); - } + val = *(u16*)(_BE_env.biosmem_base + addr - 0xC0000); + } else if (addr >= 0xA0000 && addr <= 0xFFFFF) { #ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - addr -= 0xA0000; - val = ( readb(_BE_env.busmem_base, addr) | - (readb(_BE_env.busmem_base, addr + 1) << 8)); - } - else + if (addr & 0x1) { + addr -= 0xA0000; + val = ( readb(_BE_env.busmem_base, addr) | + (readb(_BE_env.busmem_base, addr + 1) << 8)); + } + else #endif - val = readw(_BE_env.busmem_base, addr - 0xA0000); - } + val = readw(_BE_env.busmem_base, addr - 0xA0000); + } else if (addr > M.mem_size - 2) { DB( printk("mem_read: address %#lx out of range!\n", addr);) - HALT_SYS(); - } + HALT_SYS(); + } else { #ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - val = ( *(u8*)(M.mem_base + addr) | - (*(u8*)(M.mem_base + addr + 1) << 8)); - } - else + if (addr & 0x1) { + val = ( *(u8*)(M.mem_base + addr) | + (*(u8*)(M.mem_base + addr + 1) << 8)); + } + else #endif - val = *(u16*)(M.mem_base + addr); - } + val = *(u16*)(M.mem_base + addr); + } DB( if (DEBUG_MEM()) - printk("%#08x 2 -> %#x\n", addr, val);) + printk("%#08x 2 -> %#x\n", addr, val);) return val; } @@ -169,48 +169,48 @@ u32 X86API BE_rdl( if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { #ifdef __BIG_ENDIAN__ - if (addr & 0x3) { - addr -= 0xC0000; - val = ( *(u8*)(_BE_env.biosmem_base + addr + 0) | - (*(u8*)(_BE_env.biosmem_base + addr + 1) << 8) | - (*(u8*)(_BE_env.biosmem_base + addr + 2) << 16) | - (*(u8*)(_BE_env.biosmem_base + addr + 3) << 24)); - } - else + if (addr & 0x3) { + addr -= 0xC0000; + val = ( *(u8*)(_BE_env.biosmem_base + addr + 0) | + (*(u8*)(_BE_env.biosmem_base + addr + 1) << 8) | + (*(u8*)(_BE_env.biosmem_base + addr + 2) << 16) | + (*(u8*)(_BE_env.biosmem_base + addr + 3) << 24)); + } + else #endif - val = *(u32*)(_BE_env.biosmem_base + addr - 0xC0000); - } + val = *(u32*)(_BE_env.biosmem_base + addr - 0xC0000); + } else if (addr >= 0xA0000 && addr <= 0xFFFFF) { #ifdef __BIG_ENDIAN__ - if (addr & 0x3) { - addr -= 0xA0000; - val = ( readb(_BE_env.busmem_base, addr) | - (readb(_BE_env.busmem_base, addr + 1) << 8) | - (readb(_BE_env.busmem_base, addr + 2) << 16) | - (readb(_BE_env.busmem_base, addr + 3) << 24)); - } - else + if (addr & 0x3) { + addr -= 0xA0000; + val = ( readb(_BE_env.busmem_base, addr) | + (readb(_BE_env.busmem_base, addr + 1) << 8) | + (readb(_BE_env.busmem_base, addr + 2) << 16) | + (readb(_BE_env.busmem_base, addr + 3) << 24)); + } + else #endif - val = readl(_BE_env.busmem_base, addr - 0xA0000); - } + val = readl(_BE_env.busmem_base, addr - 0xA0000); + } else if (addr > M.mem_size - 4) { DB( printk("mem_read: address %#lx out of range!\n", addr);) - HALT_SYS(); - } + HALT_SYS(); + } else { #ifdef __BIG_ENDIAN__ - if (addr & 0x3) { - val = ( *(u8*)(M.mem_base + addr + 0) | - (*(u8*)(M.mem_base + addr + 1) << 8) | - (*(u8*)(M.mem_base + addr + 2) << 16) | - (*(u8*)(M.mem_base + addr + 3) << 24)); - } - else + if (addr & 0x3) { + val = ( *(u8*)(M.mem_base + addr + 0) | + (*(u8*)(M.mem_base + addr + 1) << 8) | + (*(u8*)(M.mem_base + addr + 2) << 16) | + (*(u8*)(M.mem_base + addr + 3) << 24)); + } + else #endif - val = *(u32*)(M.mem_base + addr); - } + val = *(u32*)(M.mem_base + addr); + } DB( if (DEBUG_MEM()) - printk("%#08x 4 -> %#x\n", addr, val);) + printk("%#08x 4 -> %#x\n", addr, val);) return val; } @@ -228,20 +228,20 @@ void X86API BE_wrb( u8 val) { DB( if (DEBUG_MEM()) - printk("%#08x 1 <- %#x\n", addr, val);) + printk("%#08x 1 <- %#x\n", addr, val);) if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { - *(u8*)(_BE_env.biosmem_base + addr - 0xC0000) = val; - } + *(u8*)(_BE_env.biosmem_base + addr - 0xC0000) = val; + } else if (addr >= 0xA0000 && addr <= 0xFFFFF) { - writeb(val, _BE_env.busmem_base, addr - 0xA0000); - } + writeb(val, _BE_env.busmem_base, addr - 0xA0000); + } else if (addr > M.mem_size-1) { DB( printk("mem_write: address %#lx out of range!\n", addr);) - HALT_SYS(); - } + HALT_SYS(); + } else { - *(u8*)(M.mem_base + addr) = val; - } + *(u8*)(M.mem_base + addr) = val; + } } /**************************************************************************** @@ -258,43 +258,43 @@ void X86API BE_wrw( u16 val) { DB( if (DEBUG_MEM()) - printk("%#08x 2 <- %#x\n", addr, val);) + printk("%#08x 2 <- %#x\n", addr, val);) if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { #ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - addr -= 0xC0000; - *(u8*)(_BE_env.biosmem_base + addr + 0) = (val >> 0) & 0xff; - *(u8*)(_BE_env.biosmem_base + addr + 1) = (val >> 8) & 0xff; - } - else + if (addr & 0x1) { + addr -= 0xC0000; + *(u8*)(_BE_env.biosmem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(_BE_env.biosmem_base + addr + 1) = (val >> 8) & 0xff; + } + else #endif - *(u16*)(_BE_env.biosmem_base + addr - 0xC0000) = val; - } + *(u16*)(_BE_env.biosmem_base + addr - 0xC0000) = val; + } else if (addr >= 0xA0000 && addr <= 0xFFFFF) { #ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - addr -= 0xA0000; - writeb(val >> 0, _BE_env.busmem_base, addr); - writeb(val >> 8, _BE_env.busmem_base, addr + 1); - } - else + if (addr & 0x1) { + addr -= 0xA0000; + writeb(val >> 0, _BE_env.busmem_base, addr); + writeb(val >> 8, _BE_env.busmem_base, addr + 1); + } + else #endif - writew(val, _BE_env.busmem_base, addr - 0xA0000); - } + writew(val, _BE_env.busmem_base, addr - 0xA0000); + } else if (addr > M.mem_size-2) { DB( printk("mem_write: address %#lx out of range!\n", addr);) - HALT_SYS(); - } + HALT_SYS(); + } else { #ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; - *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; - } - else + if (addr & 0x1) { + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + } + else #endif - *(u16*)(M.mem_base + addr) = val; - } + *(u16*)(M.mem_base + addr) = val; + } } /**************************************************************************** @@ -311,49 +311,49 @@ void X86API BE_wrl( u32 val) { DB( if (DEBUG_MEM()) - printk("%#08x 4 <- %#x\n", addr, val);) + printk("%#08x 4 <- %#x\n", addr, val);) if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { #ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - addr -= 0xC0000; - *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; - *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; - *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; - *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; - } - else + if (addr & 0x1) { + addr -= 0xC0000; + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; + *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; + } + else #endif - *(u32*)(M.mem_base + addr - 0xC0000) = val; - } + *(u32*)(M.mem_base + addr - 0xC0000) = val; + } else if (addr >= 0xA0000 && addr <= 0xFFFFF) { #ifdef __BIG_ENDIAN__ - if (addr & 0x3) { - addr -= 0xA0000; - writeb(val >> 0, _BE_env.busmem_base, addr); - writeb(val >> 8, _BE_env.busmem_base, addr + 1); - writeb(val >> 16, _BE_env.busmem_base, addr + 1); - writeb(val >> 24, _BE_env.busmem_base, addr + 1); - } - else + if (addr & 0x3) { + addr -= 0xA0000; + writeb(val >> 0, _BE_env.busmem_base, addr); + writeb(val >> 8, _BE_env.busmem_base, addr + 1); + writeb(val >> 16, _BE_env.busmem_base, addr + 1); + writeb(val >> 24, _BE_env.busmem_base, addr + 1); + } + else #endif - writel(val, _BE_env.busmem_base, addr - 0xA0000); - } + writel(val, _BE_env.busmem_base, addr - 0xA0000); + } else if (addr > M.mem_size-4) { DB( printk("mem_write: address %#lx out of range!\n", addr);) - HALT_SYS(); - } + HALT_SYS(); + } else { #ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; - *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; - *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; - *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; - } - else + if (addr & 0x1) { + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; + *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; + } + else #endif - *(u32*)(M.mem_base + addr) = val; - } + *(u32*)(M.mem_base + addr) = val; + } } /* Debug functions to do ISA/PCI bus port I/O */ @@ -365,7 +365,7 @@ u8 X86API BE_inb(int port) { u8 val = PM_inpb(port); if (DEBUG_IO()) - printk("%04X:%04X: inb.%04X -> %02X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + printk("%04X:%04X: inb.%04X -> %02X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); return val; } @@ -373,7 +373,7 @@ u16 X86API BE_inw(int port) { u16 val = PM_inpw(port); if (DEBUG_IO()) - printk("%04X:%04X: inw.%04X -> %04X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + printk("%04X:%04X: inw.%04X -> %04X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); return val; } @@ -381,28 +381,28 @@ u32 X86API BE_inl(int port) { u32 val = PM_inpd(port); if (DEBUG_IO()) - printk("%04X:%04X: inl.%04X -> %08X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + printk("%04X:%04X: inl.%04X -> %08X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); return val; } void X86API BE_outb(int port, u8 val) { if (DEBUG_IO()) - printk("%04X:%04X: outb.%04X <- %02X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + printk("%04X:%04X: outb.%04X <- %02X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); PM_outpb(port,val); } void X86API BE_outw(int port, u16 val) { if (DEBUG_IO()) - printk("%04X:%04X: outw.%04X <- %04X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + printk("%04X:%04X: outw.%04X <- %04X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); PM_outpw(port,val); } void X86API BE_outl(int port, u32 val) { if (DEBUG_IO()) - printk("%04X:%04X: outl.%04X <- %08X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + printk("%04X:%04X: outl.%04X <- %08X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); PM_outpd(port,val); } #endif diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/bios.c b/board/MAI/bios_emulator/scitech/src/biosemu/bios.c index 3fb4c3608a4..c0f4a4b18ea 100644 --- a/board/MAI/bios_emulator/scitech/src/biosemu/bios.c +++ b/board/MAI/bios_emulator/scitech/src/biosemu/bios.c @@ -50,9 +50,9 @@ static void X86API undefined_intr( int intno) { if (BE_rdw(intno * 4 + 2) == BIOS_SEG) - printk("biosEmu: undefined interrupt %xh called!\n",intno); + printk("biosEmu: undefined interrupt %xh called!\n",intno); else - X86EMU_prepareForInt(intno); + X86EMU_prepareForInt(intno); } /**************************************************************************** @@ -68,26 +68,26 @@ static void X86API int42( int intno) { if (M.x86.R_AH == 0x12 && M.x86.R_BL == 0x32) { - if (M.x86.R_AL == 0) { - /* Enable CPU accesses to video memory */ - PM_outpb(0x3c2, PM_inpb(0x3cc) | (u8)0x02); - return; - } - else if (M.x86.R_AL == 1) { - /* Disable CPU accesses to video memory */ - PM_outpb(0x3c2, PM_inpb(0x3cc) & (u8)~0x02); - return; - } + if (M.x86.R_AL == 0) { + /* Enable CPU accesses to video memory */ + PM_outpb(0x3c2, PM_inpb(0x3cc) | (u8)0x02); + return; + } + else if (M.x86.R_AL == 1) { + /* Disable CPU accesses to video memory */ + PM_outpb(0x3c2, PM_inpb(0x3cc) & (u8)~0x02); + return; + } #ifdef DEBUG - else { - printk("biosEmu/bios.int42: unknown function AH=0x12, BL=0x32, AL=%#02x\n",M.x86.R_AL); - } + else { + printk("biosEmu/bios.int42: unknown function AH=0x12, BL=0x32, AL=%#02x\n",M.x86.R_AL); + } #endif - } + } #ifdef DEBUG else { - printk("biosEmu/bios.int42: unknown function AH=%#02x, AL=%#02x, BL=%#02x\n",M.x86.R_AH, M.x86.R_AL, M.x86.R_BL); - } + printk("biosEmu/bios.int42: unknown function AH=%#02x, AL=%#02x, BL=%#02x\n",M.x86.R_AH, M.x86.R_AL, M.x86.R_BL); + } #endif } @@ -106,9 +106,9 @@ static void X86API int10( int intno) { if (BE_rdw(intno * 4 + 2) == BIOS_SEG) - int42(intno); + int42(intno); else - X86EMU_prepareForInt(intno); + X86EMU_prepareForInt(intno); } /* Result codes returned by the PCI BIOS */ @@ -142,87 +142,87 @@ static void X86API int1A( /* Fail if no PCI device information has been registered */ if (!_BE_env.vgaInfo.pciInfo) - return; + return; pciSlot = (u16)(_BE_env.vgaInfo.pciInfo->slot.i >> 8); switch (M.x86.R_AX) { - case 0xB101: /* PCI bios present? */ - M.x86.R_AL = 0x00; /* no config space/special cycle generation support */ - M.x86.R_EDX = 0x20494350; /* " ICP" */ - M.x86.R_BX = 0x0210; /* Version 2.10 */ - M.x86.R_CL = 0; /* Max bus number in system */ - CLEAR_FLAG(F_CF); - break; - case 0xB102: /* Find PCI device */ - M.x86.R_AH = DEVICE_NOT_FOUND; - if (M.x86.R_DX == _BE_env.vgaInfo.pciInfo->VendorID && - M.x86.R_CX == _BE_env.vgaInfo.pciInfo->DeviceID && - M.x86.R_SI == 0) { - M.x86.R_AH = SUCCESSFUL; - M.x86.R_BX = pciSlot; - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); - break; - case 0xB103: /* Find PCI class code */ - M.x86.R_AH = DEVICE_NOT_FOUND; - if (M.x86.R_CL == _BE_env.vgaInfo.pciInfo->Interface && - M.x86.R_CH == _BE_env.vgaInfo.pciInfo->SubClass && - (u8)(M.x86.R_ECX >> 16) == _BE_env.vgaInfo.pciInfo->BaseClass) { - M.x86.R_AH = SUCCESSFUL; - M.x86.R_BX = pciSlot; - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); - break; - case 0xB108: /* Read configuration byte */ - M.x86.R_AH = BAD_REGISTER_NUMBER; - if (M.x86.R_BX == pciSlot) { - M.x86.R_AH = SUCCESSFUL; - M.x86.R_CL = (u8)PCI_accessReg(M.x86.R_DI,0,PCI_READ_BYTE,_BE_env.vgaInfo.pciInfo); - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); - break; - case 0xB109: /* Read configuration word */ - M.x86.R_AH = BAD_REGISTER_NUMBER; - if (M.x86.R_BX == pciSlot) { - M.x86.R_AH = SUCCESSFUL; - M.x86.R_CX = (u16)PCI_accessReg(M.x86.R_DI,0,PCI_READ_WORD,_BE_env.vgaInfo.pciInfo); - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); - break; - case 0xB10A: /* Read configuration dword */ - M.x86.R_AH = BAD_REGISTER_NUMBER; - if (M.x86.R_BX == pciSlot) { - M.x86.R_AH = SUCCESSFUL; - M.x86.R_ECX = (u32)PCI_accessReg(M.x86.R_DI,0,PCI_READ_DWORD,_BE_env.vgaInfo.pciInfo); - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); - break; - case 0xB10B: /* Write configuration byte */ - M.x86.R_AH = BAD_REGISTER_NUMBER; - if (M.x86.R_BX == pciSlot) { - M.x86.R_AH = SUCCESSFUL; - PCI_accessReg(M.x86.R_DI,M.x86.R_CL,PCI_WRITE_BYTE,_BE_env.vgaInfo.pciInfo); - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); - break; - case 0xB10C: /* Write configuration word */ - M.x86.R_AH = BAD_REGISTER_NUMBER; - if (M.x86.R_BX == pciSlot) { - M.x86.R_AH = SUCCESSFUL; - PCI_accessReg(M.x86.R_DI,M.x86.R_CX,PCI_WRITE_WORD,_BE_env.vgaInfo.pciInfo); - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); - break; - case 0xB10D: /* Write configuration dword */ - M.x86.R_AH = BAD_REGISTER_NUMBER; - if (M.x86.R_BX == pciSlot) { - M.x86.R_AH = SUCCESSFUL; - PCI_accessReg(M.x86.R_DI,M.x86.R_ECX,PCI_WRITE_DWORD,_BE_env.vgaInfo.pciInfo); - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); - break; - default: - printk("biosEmu/bios.int1a: unknown function AX=%#04x\n", M.x86.R_AX); - } + case 0xB101: /* PCI bios present? */ + M.x86.R_AL = 0x00; /* no config space/special cycle generation support */ + M.x86.R_EDX = 0x20494350; /* " ICP" */ + M.x86.R_BX = 0x0210; /* Version 2.10 */ + M.x86.R_CL = 0; /* Max bus number in system */ + CLEAR_FLAG(F_CF); + break; + case 0xB102: /* Find PCI device */ + M.x86.R_AH = DEVICE_NOT_FOUND; + if (M.x86.R_DX == _BE_env.vgaInfo.pciInfo->VendorID && + M.x86.R_CX == _BE_env.vgaInfo.pciInfo->DeviceID && + M.x86.R_SI == 0) { + M.x86.R_AH = SUCCESSFUL; + M.x86.R_BX = pciSlot; + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB103: /* Find PCI class code */ + M.x86.R_AH = DEVICE_NOT_FOUND; + if (M.x86.R_CL == _BE_env.vgaInfo.pciInfo->Interface && + M.x86.R_CH == _BE_env.vgaInfo.pciInfo->SubClass && + (u8)(M.x86.R_ECX >> 16) == _BE_env.vgaInfo.pciInfo->BaseClass) { + M.x86.R_AH = SUCCESSFUL; + M.x86.R_BX = pciSlot; + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB108: /* Read configuration byte */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + M.x86.R_CL = (u8)PCI_accessReg(M.x86.R_DI,0,PCI_READ_BYTE,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB109: /* Read configuration word */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + M.x86.R_CX = (u16)PCI_accessReg(M.x86.R_DI,0,PCI_READ_WORD,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB10A: /* Read configuration dword */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + M.x86.R_ECX = (u32)PCI_accessReg(M.x86.R_DI,0,PCI_READ_DWORD,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB10B: /* Write configuration byte */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + PCI_accessReg(M.x86.R_DI,M.x86.R_CL,PCI_WRITE_BYTE,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB10C: /* Write configuration word */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + PCI_accessReg(M.x86.R_DI,M.x86.R_CX,PCI_WRITE_WORD,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB10D: /* Write configuration dword */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + PCI_accessReg(M.x86.R_DI,M.x86.R_ECX,PCI_WRITE_DWORD,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + default: + printk("biosEmu/bios.int1a: unknown function AX=%#04x\n", M.x86.R_AX); + } } /**************************************************************************** @@ -240,9 +240,9 @@ void _BE_bios_init( X86EMU_intrFuncs bios_intr_tab[256]; for (i = 0; i < 256; ++i) { - intrTab[i] = BIOS_SEG << 16; - bios_intr_tab[i] = undefined_intr; - } + intrTab[i] = BIOS_SEG << 16; + bios_intr_tab[i] = undefined_intr; + } bios_intr_tab[0x10] = int10; bios_intr_tab[0x1A] = int1A; bios_intr_tab[0x42] = int42; diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c b/board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c index ed2717c218e..0052709cc67 100644 --- a/board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c +++ b/board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c @@ -100,9 +100,9 @@ ibool PMAPI BE_init( #endif memset(&M,0,sizeof(M)); if (memSize < 20480) - PM_fatalError("Emulator requires at least 20Kb of memory!\n"); + PM_fatalError("Emulator requires at least 20Kb of memory!\n"); if ((M.mem_base = (unsigned long)malloc(memSize)) == NULL) - PM_fatalError("Out of memory!"); + PM_fatalError("Out of memory!"); M.mem_size = memSize; _BE_env.busmem_base = (ulong)PM_mapPhysicalAddr(0xA0000,0x5FFFF,true); M.x86.debug = debugFlags; @@ -144,15 +144,15 @@ void PMAPI BE_setVGA( _BE_env.vgaInfo.pciInfo = info->pciInfo; _BE_env.vgaInfo.BIOSImage = info->BIOSImage; if (info->BIOSImage) { - _BE_env.biosmem_base = (ulong)info->BIOSImage; - _BE_env.biosmem_limit = 0xC0000 + info->BIOSImageLen-1; - } + _BE_env.biosmem_base = (ulong)info->BIOSImage; + _BE_env.biosmem_limit = 0xC0000 + info->BIOSImageLen-1; + } else { - _BE_env.biosmem_base = _BE_env.busmem_base + 0x20000; - _BE_env.biosmem_limit = 0xC7FFF; - } + _BE_env.biosmem_base = _BE_env.busmem_base + 0x20000; + _BE_env.biosmem_limit = 0xC7FFF; + } if (*((u32*)info->LowMem) == 0) - _BE_bios_init((u32*)info->LowMem); + _BE_bios_init((u32*)info->LowMem); memcpy((u8*)M.mem_base,info->LowMem,sizeof(info->LowMem)); } @@ -182,8 +182,8 @@ This function maps a real mode pointer in the emulator memory to a protected mode pointer that can be used to directly access the memory. NOTE: The memory is *always* in little endian format, son on non-x86 - systems you will need to do endian translations to access this - memory. + systems you will need to do endian translations to access this + memory. ****************************************************************************/ void * PMAPI BE_mapRealPointer( uint r_seg, @@ -192,11 +192,11 @@ void * PMAPI BE_mapRealPointer( u32 addr = ((u32)r_seg << 4) + r_off; if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { - return (void*)(_BE_env.biosmem_base + addr - 0xC0000); - } + return (void*)(_BE_env.biosmem_base + addr - 0xC0000); + } else if (addr >= 0xA0000 && addr <= 0xFFFFF) { - return (void*)(_BE_env.busmem_base + addr - 0xA0000); - } + return (void*)(_BE_env.busmem_base + addr - 0xA0000); + } return (void*)(M.mem_base + addr); } @@ -213,8 +213,8 @@ and located at 15Kb into the start of the real mode memory (16Kb is where we put the real mode code we execute for issuing interrupts). NOTE: The memory is *always* in little endian format, son on non-x86 - systems you will need to do endian translations to access this - memory. + systems you will need to do endian translations to access this + memory. ****************************************************************************/ void * PMAPI BE_getVESABuf( uint *len, @@ -416,28 +416,28 @@ BE_exports * _CEXPORT BE_initLibrary( PM_imports *pmImp) { static BE_exports _BE_exports = { - sizeof(BE_exports), - BE_init, - BE_setVGA, - BE_getVGA, - BE_mapRealPointer, - BE_getVESABuf, - BE_callRealMode, - BE_int86, - BE_int86x, - NULL, - BE_exit, - }; + sizeof(BE_exports), + BE_init, + BE_setVGA, + BE_getVGA, + BE_mapRealPointer, + BE_getVESABuf, + BE_callRealMode, + BE_int86, + BE_int86x, + NULL, + BE_exit, + }; int i,max; ulong *p; - // Initialize all default imports to point to fatal error handler - // for upwards compatibility. + /* Initialize all default imports to point to fatal error handler */ + /* for upwards compatibility. */ max = sizeof(_PM_imports)/sizeof(BE_initLibrary_t); for (i = 0,p = (ulong*)&_PM_imports; i < max; i++) - *p++ = (ulong)_PM_fatalErrorHandler; + *p++ = (ulong)_PM_fatalErrorHandler; - // Now copy all our imported functions + /* Now copy all our imported functions */ memcpy(&_PM_imports,pmImp,MIN(sizeof(_PM_imports),pmImp->dwSize)); return &_BE_exports; } diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c b/board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c index 96fa5a0e0f2..98d5fb8a629 100644 --- a/board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c +++ b/board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c @@ -112,16 +112,16 @@ static ulong PCI_findBIOSAddr( int bar; for (bar = 0x10; bar <= 0x14; bar++) { - base = PCI_readPCIRegL(bar,device) & ~0xFF; - if (!(base & 0x1)) { - PCI_writePCIRegL(bar,0xFFFFFFFF,device); - size = PCI_readPCIRegL(bar,device) & ~0xFF; - size = ~size+1; - PCI_writePCIRegL(bar,0,device); - if (size >= MAX_BIOSLEN) - return base; - } - } + base = PCI_readPCIRegL(bar,device) & ~0xFF; + if (!(base & 0x1)) { + PCI_writePCIRegL(bar,0xFFFFFFFF,device); + size = PCI_readPCIRegL(bar,device) & ~0xFF; + size = ~size+1; + PCI_writePCIRegL(bar,0,device); + if (size >= MAX_BIOSLEN) + return base; + } + } return 0; } @@ -138,13 +138,13 @@ static void _PCI_fixupSecondaryBARs(void) int i; for (i = 0; i < NumDevices; i++) { - PCI_writePCIRegL(0x10,PCI[DeviceIndex[i]].BaseAddress10,i); - PCI_writePCIRegL(0x14,PCI[DeviceIndex[i]].BaseAddress14,i); - PCI_writePCIRegL(0x18,PCI[DeviceIndex[i]].BaseAddress18,i); - PCI_writePCIRegL(0x1C,PCI[DeviceIndex[i]].BaseAddress1C,i); - PCI_writePCIRegL(0x20,PCI[DeviceIndex[i]].BaseAddress20,i); - PCI_writePCIRegL(0x24,PCI[DeviceIndex[i]].BaseAddress24,i); - } + PCI_writePCIRegL(0x10,PCI[DeviceIndex[i]].BaseAddress10,i); + PCI_writePCIRegL(0x14,PCI[DeviceIndex[i]].BaseAddress14,i); + PCI_writePCIRegL(0x18,PCI[DeviceIndex[i]].BaseAddress18,i); + PCI_writePCIRegL(0x1C,PCI[DeviceIndex[i]].BaseAddress1C,i); + PCI_writePCIRegL(0x20,PCI[DeviceIndex[i]].BaseAddress20,i); + PCI_writePCIRegL(0x24,PCI[DeviceIndex[i]].BaseAddress24,i); + } } /**************************************************************************** @@ -165,29 +165,29 @@ static void PCI_doBIOSPOST( RMREGS regs; RMSREGS sregs; - // Determine the value to store in AX for BIOS POST + /* Determine the value to store in AX for BIOS POST */ regs.x.ax = (u16)(PCI[DeviceIndex[device]].slot.i >> 8); if (useV86) { - // Post the BIOS using the PM functions (ie: v86 mode on Linux) - if (!PM_doBIOSPOST(regs.x.ax,BIOSPhysAddr,mappedBIOS,BIOSLen)) { - // If the PM function fails, this probably means are we are on - // DOS and can't re-map the real mode 0xC0000 region. In thise - // case if the device is the primary, we can use the real - // BIOS at 0xC0000 directly. - if (device == 0) - PM_doBIOSPOST(regs.x.ax,0xC0000,mappedBIOS,BIOSLen); - } - } + /* Post the BIOS using the PM functions (ie: v86 mode on Linux) */ + if (!PM_doBIOSPOST(regs.x.ax,BIOSPhysAddr,mappedBIOS,BIOSLen)) { + /* If the PM function fails, this probably means are we are on */ + /* DOS and can't re-map the real mode 0xC0000 region. In thise */ + /* case if the device is the primary, we can use the real */ + /* BIOS at 0xC0000 directly. */ + if (device == 0) + PM_doBIOSPOST(regs.x.ax,0xC0000,mappedBIOS,BIOSLen); + } + } else { - // Setup the X86 emulator for the VGA BIOS - BE_setVGA(&VGAInfo[device]); + /* Setup the X86 emulator for the VGA BIOS */ + BE_setVGA(&VGAInfo[device]); - // Execute the BIOS POST code - BE_callRealMode(0xC000,0x0003,®s,&sregs); + /* Execute the BIOS POST code */ + BE_callRealMode(0xC000,0x0003,®s,&sregs); - // Cleanup and exit - BE_getVGA(&VGAInfo[device]); - } + /* Cleanup and exit */ + BE_getVGA(&VGAInfo[device]); + } } /**************************************************************************** @@ -206,113 +206,113 @@ static ibool PCI_postControllers(void) char filename[_MAX_PATH]; FILE *f; - // Disable the primary display controller and AGP VGA pass-through + /* Disable the primary display controller and AGP VGA pass-through */ DISABLE_DEVICE(0); if (AGPBridge) - DISABLE_AGP_VGA(); + DISABLE_AGP_VGA(); - // Now POST all the secondary controllers + /* Now POST all the secondary controllers */ for (device = 0; device < NumDevices; device++) { - // Skip the device if it is not enabled (probably an ISA device) - if (DeviceIndex[device] == -1) - continue; - - // Enable secondary display controller. If the secondary controller - // is on the AGP bus, then enable VGA resources for the AGP device. - ENABLE_DEVICE(device); - if (AGPBridge && AGPBridge->SecondayBusNumber == PCI[DeviceIndex[device]].slot.p.Bus) - ENABLE_AGP_VGA(); - - // Check if the controller has already been POST'ed - if (VGA_NOT_ACTIVE()) { - // Find a viable place to map the secondary PCI BIOS image and map it - printk("Device %d not enabled, so attempting warm boot it\n", device); - - // For AGP devices (and PCI devices that do have the ROM base - // address zero'ed out) we have to map the BIOS to a location - // that is passed by the AGP bridge to the bus. Some AGP devices - // have the ROM base address already set up for us, and some - // do not (we map to one of the existing BAR locations in - // this case). - mappedBIOS = NULL; - if (PCI[DeviceIndex[device]].ROMBaseAddress != 0) - mappedBIOSPhys = PCI[DeviceIndex[device]].ROMBaseAddress & ~0xF; - else - mappedBIOSPhys = PCI_findBIOSAddr(device); - printk("Mapping BIOS image to 0x%08X\n", mappedBIOSPhys); - mappedBIOS = PM_mapPhysicalAddr(mappedBIOSPhys,MAX_BIOSLEN-1,false); - PCI_writePCIRegL(0x30,mappedBIOSPhys | 0x1,device); - BIOSImageLen = mappedBIOS[2] * 512; - if ((copyOfBIOS = malloc(BIOSImageLen)) == NULL) - return false; - memcpy(copyOfBIOS,mappedBIOS,BIOSImageLen); - PM_freePhysicalAddr(mappedBIOS,MAX_BIOSLEN-1); - - // Allocate memory to store copy of BIOS from secondary controllers - VGAInfo[device].pciInfo = &PCI[DeviceIndex[device]]; - VGAInfo[device].BIOSImage = copyOfBIOS; - VGAInfo[device].BIOSImageLen = BIOSImageLen; - - // Restore device mappings - PCI_writePCIRegL(0x30,PCI[DeviceIndex[device]].ROMBaseAddress,device); - PCI_writePCIRegL(0x10,PCI[DeviceIndex[device]].BaseAddress10,device); - PCI_writePCIRegL(0x14,PCI[DeviceIndex[device]].BaseAddress14,device); - - // Now execute the BIOS POST for the device - if (copyOfBIOS[0] == 0x55 && copyOfBIOS[1] == 0xAA) { - printk("Executing BIOS POST for controller.\n"); - PCI_doBIOSPOST(device,mappedBIOSPhys,copyOfBIOS,BIOSImageLen); - } - - // Reset the size of the BIOS image to the final size - VGAInfo[device].BIOSImageLen = FINAL_BIOSLEN; - - // Save the BIOS and interrupt vector information to disk - sprintf(filename,"%s/bios.%02d",PM_getNucleusConfigPath(),device); - if ((f = fopen(filename,"wb")) != NULL) { - fwrite(copyOfBIOS,1,FINAL_BIOSLEN,f); - fwrite(VGAInfo[device].LowMem,1,sizeof(VGAInfo[device].LowMem),f); - fclose(f); - } - } - else { - // Allocate memory to store copy of BIOS from secondary controllers - if ((copyOfBIOS = malloc(FINAL_BIOSLEN)) == NULL) - return false; - VGAInfo[device].pciInfo = &PCI[DeviceIndex[device]]; - VGAInfo[device].BIOSImage = copyOfBIOS; - VGAInfo[device].BIOSImageLen = FINAL_BIOSLEN; - - // Load the BIOS and interrupt vector information from disk - sprintf(filename,"%s/bios.%02d",PM_getNucleusConfigPath(),device); - if ((f = fopen(filename,"rb")) != NULL) { - fread(copyOfBIOS,1,FINAL_BIOSLEN,f); - fread(VGAInfo[device].LowMem,1,sizeof(VGAInfo[device].LowMem),f); - fclose(f); - } - } - - // Fix up all the secondary PCI base address registers - // (restores them all from the values we read previously) - _PCI_fixupSecondaryBARs(); - - // Disable the secondary controller and AGP VGA pass-through - DISABLE_DEVICE(device); - if (AGPBridge) - DISABLE_AGP_VGA(); - } - - // Reenable primary display controller and reset AGP bridge control + /* Skip the device if it is not enabled (probably an ISA device) */ + if (DeviceIndex[device] == -1) + continue; + + /* Enable secondary display controller. If the secondary controller */ + /* is on the AGP bus, then enable VGA resources for the AGP device. */ + ENABLE_DEVICE(device); + if (AGPBridge && AGPBridge->SecondayBusNumber == PCI[DeviceIndex[device]].slot.p.Bus) + ENABLE_AGP_VGA(); + + /* Check if the controller has already been POST'ed */ + if (VGA_NOT_ACTIVE()) { + /* Find a viable place to map the secondary PCI BIOS image and map it */ + printk("Device %d not enabled, so attempting warm boot it\n", device); + + /* For AGP devices (and PCI devices that do have the ROM base */ + /* address zero'ed out) we have to map the BIOS to a location */ + /* that is passed by the AGP bridge to the bus. Some AGP devices */ + /* have the ROM base address already set up for us, and some */ + /* do not (we map to one of the existing BAR locations in */ + /* this case). */ + mappedBIOS = NULL; + if (PCI[DeviceIndex[device]].ROMBaseAddress != 0) + mappedBIOSPhys = PCI[DeviceIndex[device]].ROMBaseAddress & ~0xF; + else + mappedBIOSPhys = PCI_findBIOSAddr(device); + printk("Mapping BIOS image to 0x%08X\n", mappedBIOSPhys); + mappedBIOS = PM_mapPhysicalAddr(mappedBIOSPhys,MAX_BIOSLEN-1,false); + PCI_writePCIRegL(0x30,mappedBIOSPhys | 0x1,device); + BIOSImageLen = mappedBIOS[2] * 512; + if ((copyOfBIOS = malloc(BIOSImageLen)) == NULL) + return false; + memcpy(copyOfBIOS,mappedBIOS,BIOSImageLen); + PM_freePhysicalAddr(mappedBIOS,MAX_BIOSLEN-1); + + /* Allocate memory to store copy of BIOS from secondary controllers */ + VGAInfo[device].pciInfo = &PCI[DeviceIndex[device]]; + VGAInfo[device].BIOSImage = copyOfBIOS; + VGAInfo[device].BIOSImageLen = BIOSImageLen; + + /* Restore device mappings */ + PCI_writePCIRegL(0x30,PCI[DeviceIndex[device]].ROMBaseAddress,device); + PCI_writePCIRegL(0x10,PCI[DeviceIndex[device]].BaseAddress10,device); + PCI_writePCIRegL(0x14,PCI[DeviceIndex[device]].BaseAddress14,device); + + /* Now execute the BIOS POST for the device */ + if (copyOfBIOS[0] == 0x55 && copyOfBIOS[1] == 0xAA) { + printk("Executing BIOS POST for controller.\n"); + PCI_doBIOSPOST(device,mappedBIOSPhys,copyOfBIOS,BIOSImageLen); + } + + /* Reset the size of the BIOS image to the final size */ + VGAInfo[device].BIOSImageLen = FINAL_BIOSLEN; + + /* Save the BIOS and interrupt vector information to disk */ + sprintf(filename,"%s/bios.%02d",PM_getNucleusConfigPath(),device); + if ((f = fopen(filename,"wb")) != NULL) { + fwrite(copyOfBIOS,1,FINAL_BIOSLEN,f); + fwrite(VGAInfo[device].LowMem,1,sizeof(VGAInfo[device].LowMem),f); + fclose(f); + } + } + else { + /* Allocate memory to store copy of BIOS from secondary controllers */ + if ((copyOfBIOS = malloc(FINAL_BIOSLEN)) == NULL) + return false; + VGAInfo[device].pciInfo = &PCI[DeviceIndex[device]]; + VGAInfo[device].BIOSImage = copyOfBIOS; + VGAInfo[device].BIOSImageLen = FINAL_BIOSLEN; + + /* Load the BIOS and interrupt vector information from disk */ + sprintf(filename,"%s/bios.%02d",PM_getNucleusConfigPath(),device); + if ((f = fopen(filename,"rb")) != NULL) { + fread(copyOfBIOS,1,FINAL_BIOSLEN,f); + fread(VGAInfo[device].LowMem,1,sizeof(VGAInfo[device].LowMem),f); + fclose(f); + } + } + + /* Fix up all the secondary PCI base address registers */ + /* (restores them all from the values we read previously) */ + _PCI_fixupSecondaryBARs(); + + /* Disable the secondary controller and AGP VGA pass-through */ + DISABLE_DEVICE(device); + if (AGPBridge) + DISABLE_AGP_VGA(); + } + + /* Reenable primary display controller and reset AGP bridge control */ if (AGPBridge) - RESTORE_AGP_VGA(); + RESTORE_AGP_VGA(); ENABLE_DEVICE(0); - // Free physical BIOS image mapping + /* Free physical BIOS image mapping */ PM_freePhysicalAddr(mappedBIOS,MAX_BIOSLEN-1); - // Restore the X86 emulator BIOS info to primary controller + /* Restore the X86 emulator BIOS info to primary controller */ if (!useV86) - BE_setVGA(&VGAInfo[0]); + BE_setVGA(&VGAInfo[0]); return true; } @@ -327,123 +327,123 @@ static void EnumeratePCI(void) PCIBridgeInfo *info; printk("Displaying enumeration of PCI bus (%d devices, %d display devices)\n", - NumPCI, NumDevices); + NumPCI, NumDevices); for (index = 0; index < NumDevices; index++) - printk(" Display device %d is PCI device %d\n",index,DeviceIndex[index]); + printk(" Display device %d is PCI device %d\n",index,DeviceIndex[index]); printk("\n"); printk("Bus Slot Fnc DeviceID SubSystem Rev Class IRQ Int Cmd\n"); for (i = 0; i < NumPCI; i++) { - printk("%2d %2d %2d %04X:%04X %04X:%04X %02X %02X:%02X %02X %02X %04X ", - PCI[i].slot.p.Bus, - PCI[i].slot.p.Device, - PCI[i].slot.p.Function, - PCI[i].VendorID, - PCI[i].DeviceID, - PCI[i].SubSystemVendorID, - PCI[i].SubSystemID, - PCI[i].RevID, - PCI[i].BaseClass, - PCI[i].SubClass, - PCI[i].InterruptLine, - PCI[i].InterruptPin, - PCI[i].Command); - for (index = 0; index < NumDevices; index++) { - if (DeviceIndex[index] == i) - break; - } - if (index < NumDevices) - printk("<- %d\n", index); - else - printk("\n"); - } + printk("%2d %2d %2d %04X:%04X %04X:%04X %02X %02X:%02X %02X %02X %04X ", + PCI[i].slot.p.Bus, + PCI[i].slot.p.Device, + PCI[i].slot.p.Function, + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].SubSystemVendorID, + PCI[i].SubSystemID, + PCI[i].RevID, + PCI[i].BaseClass, + PCI[i].SubClass, + PCI[i].InterruptLine, + PCI[i].InterruptPin, + PCI[i].Command); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printk("<- %d\n", index); + else + printk("\n"); + } printk("\n"); printk("DeviceID Stat Ifc Cch Lat Hdr BIST\n"); for (i = 0; i < NumPCI; i++) { - printk("%04X:%04X %04X %02X %02X %02X %02X %02X ", - PCI[i].VendorID, - PCI[i].DeviceID, - PCI[i].Status, - PCI[i].Interface, - PCI[i].CacheLineSize, - PCI[i].LatencyTimer, - PCI[i].HeaderType, - PCI[i].BIST); - for (index = 0; index < NumDevices; index++) { - if (DeviceIndex[index] == i) - break; - } - if (index < NumDevices) - printk("<- %d\n", index); - else - printk("\n"); - } + printk("%04X:%04X %04X %02X %02X %02X %02X %02X ", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].Status, + PCI[i].Interface, + PCI[i].CacheLineSize, + PCI[i].LatencyTimer, + PCI[i].HeaderType, + PCI[i].BIST); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printk("<- %d\n", index); + else + printk("\n"); + } printk("\n"); printk("DeviceID Base10h Base14h Base18h Base1Ch Base20h Base24h ROMBase\n"); for (i = 0; i < NumPCI; i++) { - printk("%04X:%04X %08X %08X %08X %08X %08X %08X %08X ", - PCI[i].VendorID, - PCI[i].DeviceID, - PCI[i].BaseAddress10, - PCI[i].BaseAddress14, - PCI[i].BaseAddress18, - PCI[i].BaseAddress1C, - PCI[i].BaseAddress20, - PCI[i].BaseAddress24, - PCI[i].ROMBaseAddress); - for (index = 0; index < NumDevices; index++) { - if (DeviceIndex[index] == i) - break; - } - if (index < NumDevices) - printk("<- %d\n", index); - else - printk("\n"); - } + printk("%04X:%04X %08X %08X %08X %08X %08X %08X %08X ", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].BaseAddress10, + PCI[i].BaseAddress14, + PCI[i].BaseAddress18, + PCI[i].BaseAddress1C, + PCI[i].BaseAddress20, + PCI[i].BaseAddress24, + PCI[i].ROMBaseAddress); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printk("<- %d\n", index); + else + printk("\n"); + } printk("\n"); printk("DeviceID BAR10Len BAR14Len BAR18Len BAR1CLen BAR20Len BAR24Len ROMLen\n"); for (i = 0; i < NumPCI; i++) { - printk("%04X:%04X %08X %08X %08X %08X %08X %08X %08X ", - PCI[i].VendorID, - PCI[i].DeviceID, - PCI[i].BaseAddress10Len, - PCI[i].BaseAddress14Len, - PCI[i].BaseAddress18Len, - PCI[i].BaseAddress1CLen, - PCI[i].BaseAddress20Len, - PCI[i].BaseAddress24Len, - PCI[i].ROMBaseAddressLen); - for (index = 0; index < NumDevices; index++) { - if (DeviceIndex[index] == i) - break; - } - if (index < NumDevices) - printk("<- %d\n", index); - else - printk("\n"); - } + printk("%04X:%04X %08X %08X %08X %08X %08X %08X %08X ", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].BaseAddress10Len, + PCI[i].BaseAddress14Len, + PCI[i].BaseAddress18Len, + PCI[i].BaseAddress1CLen, + PCI[i].BaseAddress20Len, + PCI[i].BaseAddress24Len, + PCI[i].ROMBaseAddressLen); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printk("<- %d\n", index); + else + printk("\n"); + } printk("\n"); printk("Displaying enumeration of %d bridge devices\n",NumBridges); printk("\n"); printk("DeviceID P# S# B# IOB IOL MemBase MemLimit PreBase PreLimit Ctrl\n"); for (i = 0; i < NumBridges; i++) { - info = (PCIBridgeInfo*)&PCI[BridgeIndex[i]]; - printk("%04X:%04X %02X %02X %02X %04X %04X %08X %08X %08X %08X %04X\n", - info->VendorID, - info->DeviceID, - info->PrimaryBusNumber, - info->SecondayBusNumber, - info->SubordinateBusNumber, - ((u16)info->IOBase << 8) & 0xF000, - info->IOLimit ? - ((u16)info->IOLimit << 8) | 0xFFF : 0, - ((u32)info->MemoryBase << 16) & 0xFFF00000, - info->MemoryLimit ? - ((u32)info->MemoryLimit << 16) | 0xFFFFF : 0, - ((u32)info->PrefetchableMemoryBase << 16) & 0xFFF00000, - info->PrefetchableMemoryLimit ? - ((u32)info->PrefetchableMemoryLimit << 16) | 0xFFFFF : 0, - info->BridgeControl); - } + info = (PCIBridgeInfo*)&PCI[BridgeIndex[i]]; + printk("%04X:%04X %02X %02X %02X %04X %04X %08X %08X %08X %08X %04X\n", + info->VendorID, + info->DeviceID, + info->PrimaryBusNumber, + info->SecondayBusNumber, + info->SubordinateBusNumber, + ((u16)info->IOBase << 8) & 0xF000, + info->IOLimit ? + ((u16)info->IOLimit << 8) | 0xFFF : 0, + ((u32)info->MemoryBase << 16) & 0xFFF00000, + info->MemoryLimit ? + ((u32)info->MemoryLimit << 16) | 0xFFFFF : 0, + ((u32)info->PrefetchableMemoryBase << 16) & 0xFFF00000, + info->PrefetchableMemoryLimit ? + ((u32)info->PrefetchableMemoryLimit << 16) | 0xFFFFF : 0, + info->BridgeControl); + } printk("\n"); } @@ -460,51 +460,51 @@ static int PCI_enumerateDevices(void) int i,j; PCIBridgeInfo *info; - // If this is the first time we have been called, enumerate all - // devices on the PCI bus. + /* If this is the first time we have been called, enumerate all */ + /* devices on the PCI bus. */ if (NumPCI == -1) { - for (i = 0; i < MAX_PCI_DEVICES; i++) - PCI[i].dwSize = sizeof(PCI[i]); - if ((NumPCI = PCI_enumerate(PCI,MAX_PCI_DEVICES)) == 0) - return -1; - - // Build a list of all PCI bridge devices - for (i = 0,NumBridges = 0,BridgeIndex[0] = -1; i < NumPCI; i++) { - if (PCI[i].BaseClass == PCI_BRIDGE_CLASS) { - if (NumBridges < MAX_PCI_DEVICES) - BridgeIndex[NumBridges++] = i; - } - } - - // Now build a list of all display class devices - for (i = 0,NumDevices = 1,DeviceIndex[0] = -1; i < NumPCI; i++) { - if (PCI_IS_DISPLAY_CLASS(&PCI[i])) { - if ((PCI[i].Command & 0x3) == 0x3) { - DeviceIndex[0] = i; - } - else { - if (NumDevices < MAX_PCI_DEVICES) - DeviceIndex[NumDevices++] = i; - } - if (PCI[i].slot.p.Bus != 0) { - // This device is on a different bus than the primary - // PCI bus, so it is probably an AGP device. Find the - // AGP bus device that controls that bus so we can - // control it. - for (j = 0; j < NumBridges; j++) { - info = (PCIBridgeInfo*)&PCI[BridgeIndex[j]]; - if (info->SecondayBusNumber == PCI[i].slot.p.Bus) { - AGPBridge = info; - break; - } - } - } - } - } - - // Enumerate all PCI and bridge devices to log file - EnumeratePCI(); - } + for (i = 0; i < MAX_PCI_DEVICES; i++) + PCI[i].dwSize = sizeof(PCI[i]); + if ((NumPCI = PCI_enumerate(PCI,MAX_PCI_DEVICES)) == 0) + return -1; + + /* Build a list of all PCI bridge devices */ + for (i = 0,NumBridges = 0,BridgeIndex[0] = -1; i < NumPCI; i++) { + if (PCI[i].BaseClass == PCI_BRIDGE_CLASS) { + if (NumBridges < MAX_PCI_DEVICES) + BridgeIndex[NumBridges++] = i; + } + } + + /* Now build a list of all display class devices */ + for (i = 0,NumDevices = 1,DeviceIndex[0] = -1; i < NumPCI; i++) { + if (PCI_IS_DISPLAY_CLASS(&PCI[i])) { + if ((PCI[i].Command & 0x3) == 0x3) { + DeviceIndex[0] = i; + } + else { + if (NumDevices < MAX_PCI_DEVICES) + DeviceIndex[NumDevices++] = i; + } + if (PCI[i].slot.p.Bus != 0) { + /* This device is on a different bus than the primary */ + /* PCI bus, so it is probably an AGP device. Find the */ + /* AGP bus device that controls that bus so we can */ + /* control it. */ + for (j = 0; j < NumBridges; j++) { + info = (PCIBridgeInfo*)&PCI[BridgeIndex[j]]; + if (info->SecondayBusNumber == PCI[i].slot.p.Bus) { + AGPBridge = info; + break; + } + } + } + } + } + + /* Enumerate all PCI and bridge devices to log file */ + EnumeratePCI(); + } return NumDevices; } @@ -522,48 +522,48 @@ void printk(const char *fmt, ...) int main(int argc,char *argv[]) { while (argc > 1) { - if (stricmp(argv[1],"-usev86") == 0) { - useV86 = true; - } - else if (stricmp(argv[1],"-force") == 0) { - forcePost = true; - } + if (stricmp(argv[1],"-usev86") == 0) { + useV86 = true; + } + else if (stricmp(argv[1],"-force") == 0) { + forcePost = true; + } #ifdef DEBUG - else if (stricmp(argv[1],"-decode") == 0) { - debugFlags |= DEBUG_DECODE_F; - } - else if (stricmp(argv[1],"-iotrace") == 0) { - debugFlags |= DEBUG_IO_TRACE_F; - } + else if (stricmp(argv[1],"-decode") == 0) { + debugFlags |= DEBUG_DECODE_F; + } + else if (stricmp(argv[1],"-iotrace") == 0) { + debugFlags |= DEBUG_IO_TRACE_F; + } #endif - else { - printf("Usage: warmboot [-usev86] [-force] [-decode] [-iotrace]\n"); - exit(-1); - } - argc--; - argv++; - } + else { + printf("Usage: warmboot [-usev86] [-force] [-decode] [-iotrace]\n"); + exit(-1); + } + argc--; + argv++; + } if ((logfile = fopen("warmboot.log","w")) == NULL) - exit(1); + exit(1); PM_init(); if (!useV86) { - // Initialise the x86 BIOS emulator - BE_init(false,debugFlags,65536,&VGAInfo[0]); - } + /* Initialise the x86 BIOS emulator */ + BE_init(false,debugFlags,65536,&VGAInfo[0]); + } - // Enumerate all devices (which POST's them at the same time) + /* Enumerate all devices (which POST's them at the same time) */ if (PCI_enumerateDevices() < 1) { - printk("No PCI display devices found!\n"); - return -1; - } + printk("No PCI display devices found!\n"); + return -1; + } - // Post all the display controller BIOS'es + /* Post all the display controller BIOS'es */ PCI_postControllers(); - // Cleanup and exit the emulator + /* Cleanup and exit the emulator */ if (!useV86) - BE_exit(); + BE_exit(); fclose(logfile); return 0; } |