1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
|
/*
* This code was extracted from:
* git://github.com/gonzoua/u-boot-pi.git master
* and hence presumably (C) 2012 Oleksandr Tymoshenko
*
* Tweaks for U-Boot upstreaming
* (C) 2012 Stephen Warren
*
* Portions (e.g. read/write macros, concepts for back-to-back register write
* timing workarounds) obviously extracted from the Linux kernel at:
* https://github.com/raspberrypi/linux.git rpi-3.6.y
*
* The Linux kernel code has the following (c) and license, which is hence
* propagated to Oleksandr's tree and here:
*
* Support for SDHCI device on 2835
* Based on sdhci-bcm2708.c (c) 2010 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/* Supports:
* SDHCI platform device - Arasan SD controller in BCM2708
*
* Inspired by sdhci-pci.c, by Pierre Ossman
*/
#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <memalign.h>
#include <sdhci.h>
#include <asm/arch/msg.h>
#include <asm/arch/mbox.h>
#include <mach/sdhci.h>
#include <mach/timer.h>
/* 400KHz is max freq for card ID etc. Use that as min */
#define MIN_FREQ 400000
#define SDHCI_BUFFER 0x20
struct bcm2835_sdhci_plat {
struct mmc_config cfg;
struct mmc mmc;
};
struct bcm2835_sdhci_host {
struct sdhci_host host;
uint twoticks_delay;
ulong last_write;
};
static inline struct bcm2835_sdhci_host *to_bcm(struct sdhci_host *host)
{
return (struct bcm2835_sdhci_host *)host;
}
static inline void bcm2835_sdhci_raw_writel(struct sdhci_host *host, u32 val,
int reg)
{
struct bcm2835_sdhci_host *bcm_host = to_bcm(host);
/*
* The Arasan has a bugette whereby it may lose the content of
* successive writes to registers that are within two SD-card clock
* cycles of each other (a clock domain crossing problem).
* It seems, however, that the data register does not have this problem.
* (Which is just as well - otherwise we'd have to nobble the DMA engine
* too)
*/
if (reg != SDHCI_BUFFER) {
while (timer_get_us() - bcm_host->last_write <
bcm_host->twoticks_delay)
;
}
writel(val, host->ioaddr + reg);
bcm_host->last_write = timer_get_us();
}
static inline u32 bcm2835_sdhci_raw_readl(struct sdhci_host *host, int reg)
{
return readl(host->ioaddr + reg);
}
static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
bcm2835_sdhci_raw_writel(host, val, reg);
}
static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
static u32 shadow;
u32 oldval = (reg == SDHCI_COMMAND) ? shadow :
bcm2835_sdhci_raw_readl(host, reg & ~3);
u32 word_num = (reg >> 1) & 1;
u32 word_shift = word_num * 16;
u32 mask = 0xffff << word_shift;
u32 newval = (oldval & ~mask) | (val << word_shift);
if (reg == SDHCI_TRANSFER_MODE)
shadow = newval;
else
bcm2835_sdhci_raw_writel(host, newval, reg & ~3);
}
static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
{
u32 oldval = bcm2835_sdhci_raw_readl(host, reg & ~3);
u32 byte_num = reg & 3;
u32 byte_shift = byte_num * 8;
u32 mask = 0xff << byte_shift;
u32 newval = (oldval & ~mask) | (val << byte_shift);
bcm2835_sdhci_raw_writel(host, newval, reg & ~3);
}
static u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
{
u32 val = bcm2835_sdhci_raw_readl(host, reg);
return val;
}
static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg)
{
u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3));
u32 word_num = (reg >> 1) & 1;
u32 word_shift = word_num * 16;
u32 word = (val >> word_shift) & 0xffff;
return word;
}
static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
{
u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3));
u32 byte_num = reg & 3;
u32 byte_shift = byte_num * 8;
u32 byte = (val >> byte_shift) & 0xff;
return byte;
}
static const struct sdhci_ops bcm2835_ops = {
.write_l = bcm2835_sdhci_writel,
.write_w = bcm2835_sdhci_writew,
.write_b = bcm2835_sdhci_writeb,
.read_l = bcm2835_sdhci_readl,
.read_w = bcm2835_sdhci_readw,
.read_b = bcm2835_sdhci_readb,
};
static int bcm2835_sdhci_bind(struct udevice *dev)
{
struct bcm2835_sdhci_plat *plat = dev_get_platdata(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
static int bcm2835_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct bcm2835_sdhci_plat *plat = dev_get_platdata(dev);
struct bcm2835_sdhci_host *priv = dev_get_priv(dev);
struct sdhci_host *host = &priv->host;
fdt_addr_t base;
int emmc_freq;
int ret;
base = devfdt_get_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
ret = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_EMMC);
if (ret < 0) {
debug("%s: Failed to set MMC clock (err=%d)\n", __func__, ret);
return ret;
}
emmc_freq = ret;
/*
* See the comments in bcm2835_sdhci_raw_writel().
*
* This should probably be dynamically calculated based on the actual
* frequency. However, this is the longest we'll have to wait, and
* doesn't seem to slow access down too much, so the added complexity
* doesn't seem worth it for now.
*
* 1/MIN_FREQ is (max) time per tick of eMMC clock.
* 2/MIN_FREQ is time for two ticks.
* Multiply by 1000000 to get uS per two ticks.
* +1 for hack rounding.
*/
priv->twoticks_delay = ((2 * 1000000) / MIN_FREQ) + 1;
priv->last_write = 0;
host->name = dev->name;
host->ioaddr = (void *)base;
host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B |
SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT;
host->max_clk = emmc_freq;
host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
host->ops = &bcm2835_ops;
ret = sdhci_setup_cfg(&plat->cfg, host, emmc_freq, MIN_FREQ);
if (ret) {
debug("%s: Failed to setup SDHCI (err=%d)\n", __func__, ret);
return ret;
}
upriv->mmc = &plat->mmc;
host->mmc = &plat->mmc;
host->mmc->priv = host;
return sdhci_probe(dev);
}
static const struct udevice_id bcm2835_sdhci_match[] = {
{ .compatible = "brcm,bcm2835-sdhci" },
{ /* sentinel */ }
};
U_BOOT_DRIVER(sdhci_cdns) = {
.name = "sdhci-bcm2835",
.id = UCLASS_MMC,
.of_match = bcm2835_sdhci_match,
.bind = bcm2835_sdhci_bind,
.probe = bcm2835_sdhci_probe,
.priv_auto_alloc_size = sizeof(struct bcm2835_sdhci_host),
.platdata_auto_alloc_size = sizeof(struct bcm2835_sdhci_plat),
.ops = &sdhci_ops,
};
|
