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Diffstat (limited to 'arch/arm/plat-mxs/include')
24 files changed, 2690 insertions, 0 deletions
diff --git a/arch/arm/plat-mxs/include/mach/arc_otg.h b/arch/arm/plat-mxs/include/mach/arc_otg.h new file mode 100644 index 000000000000..5ba352f90fbe --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/arc_otg.h @@ -0,0 +1,174 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MXC_ARC_OTG_H__ +#define __ASM_ARCH_MXC_ARC_OTG_H__ + +#include "../../regs-usbphy.h" +#if defined(CONFIG_USB_STATIC_IRAM) \ + || defined(CONFIG_USB_STATIC_IRAM_PPH) +#define USB_IRAM_SIZE SZ_8K +#else +#define USB_IRAM_SIZE 0 +#endif + +#define OTG_BASE_ADDR USBCTRL0_PHYS_ADDR +#define USB_OTGREGS_BASE (OTG_BASE_ADDR + 0x000) +/* + * OTG registers + */ +#define UOG_ID (0x00) /* Host ID */ +#define UOG_HWGENERAL (0x04) /* Host General */ +#define UOG_HWHOST (0x08) /* Host h/w params */ +#define UOG_HWTXBUF (0x10) /* TX buffer h/w params */ +#define UOG_HWRXBUF (0x14) /* RX buffer h/w params */ +#define UOG_CAPLENGTH (0x100) /* Capability register length */ +#define UOG_HCIVERSION (0x102) /* Host Interface version */ +#define UOG_HCSPARAMS (0x104) /* Host control structural params */ +#define UOG_HCCPARAMS (0x108) /* control capability params */ +#define UOG_DCIVERSION (0x120) /* device interface version */ +/* start EHCI registers: */ +#define UOG_USBCMD (0x140) /* USB command register */ +#define UOG_USBSTS (0x144) /* USB status register */ +#define UOG_USBINTR (0x148) /* interrupt enable register */ +#define UOG_FRINDEX (0x14c) /* USB frame index */ +/* segment (0x150) addr bits 63:32 if needed */ +#define UOG_PERIODICLISTBASE (0x154) /* host crtlr frame list base addr */ +#define UOG_DEVICEADDR (0x154) /* device crtlr device address */ +#define UOG_ASYNCLISTADDR (0x158) /* host ctrlr next async addr */ +#define UOG_EPLISTADDR (0x158) /* device ctrlr endpoint list addr */ +#define UOG_BURSTSIZE (0x160) /* host ctrlr embedded TT + async buf status */ +#define UOG_TXFILLTUNING (0x164) /* TX FIFO fill tuning */ +#define UOG_ULPIVIEW (0x170) /* ULPI viewport */ +#define UOG_CFGFLAG (0x180) /* configflag (supports HS) */ +#define UOG_PORTSC1 (0x184) /* port status and control */ +/* end EHCI registers: */ +#define UOG_OTGSC (0x1a4) /* OTG status and control */ +#define UOG_USBMODE (0x1a8) /* USB device mode */ +#define UOG_ENDPTSETUPSTAT (0x1ac) /* endpoint setup status */ +#define UOG_ENDPTPRIME (0x1b0) /* endpoint initialization */ +#define UOG_ENDPTFLUSH (0x1b4) /* endpoint de-initialize */ +#define UOG_ENDPTSTAT (0x1b8) /* endpoint status */ +#define UOG_ENDPTCOMPLETE (0x1bc) /* endpoint complete */ +#define UOG_EPCTRL0 (0x1c0) /* endpoint control0 */ +/* + * register bits + */ + +/* x_PORTSCx */ +#define PORTSC_PTS_MASK (3 << 30) /* parallel xcvr mask */ +#define PORTSC_PTS_UTMI (0 << 30) /* UTMI/UTMI+ */ +#define PORTSC_PTS_PHILIPS (1 << 30) /* Philips classic */ +#define PORTSC_PTS_ULPI (2 << 30) /* ULPI */ +#define PORTSC_PTS_SERIAL (3 << 30) /* serial */ +#define PORTSC_STS (1 << 29) /* serial xcvr select */ +#define PORTSC_PTW (1 << 28) /* UTMI width */ +#define PORTSC_PHCD (1 << 23) /* Low Power Suspend */ +#define PORTSC_PORT_POWER (1 << 12) /* port power */ +#define PORTSC_LS_MASK (3 << 10) /* Line State mask */ +#define PORTSC_LS_SE0 (0 << 10) /* SE0 */ +#define PORTSC_LS_K_STATE (1 << 10) /* K-state */ +#define PORTSC_LS_J_STATE (2 << 10) /* J-state */ +#define PORTSC_PORT_RESET (1 << 8) /* Port reset */ +#define PORTSC_PORT_SUSPEND (1 << 7) /* Suspend */ +#define PORTSC_PORT_FORCE_RESUME (1 << 6) /* Force port resume */ +#define PORTSC_OVER_CURRENT_CHG (1 << 5) /* over current change */ +#define PORTSC_OVER_CURRENT_ACT (1 << 4) /* over currrent active */ +#define PORTSC_PORT_EN_DIS_CHANGE (1 << 3) /* port change */ +#define PORTSC_PORT_ENABLE (1 << 2) /* port enabled */ +#define PORTSC_CONNECT_STATUS_CHANGE (1 << 1) /* connect status change */ +#define PORTSC_CURRENT_CONNECT_STATUS (1 << 0) /* current connect status */ + +#define PORTSC_W1C_BITS \ + (PORTSC_CONNECT_STATUS_CHANGE | \ + PORTSC_PORT_EN_DIS_CHANGE | \ + PORTSC_OVER_CURRENT_CHG) + +/* UOG_OTGSC Register Bits */ +/* control bits: */ +#define OTGSC_CTRL_VBUS_DISCHARGE (1 << 0) +#define OTGSC_CTRL_VBUS_CHARGE (1 << 1) +/* controls DM pulldown */ +#define OTGSC_CTRL_OTG_TERM (1 << 3) +#define OTGSC_CTRL_DATA_PULSING (1 << 4) +#define OTGSC_CTRL_USB_ID_PU (1 << 5) +/* current status: (R/O) */ +/* 0=A-device 1=B-device */ +#define OTGSC_STS_USB_ID (1 << 8) +#define OTGSC_STS_A_VBUS_VALID (1 << 9) +#define OTGSC_STS_A_SESSION_VALID (1 << 10) +#define OTGSC_STS_B_SESSION_VALID (1 << 11) +#define OTGSC_STS_B_SESSION_END (1 << 12) +#define OTGSC_STS_1ms_TIMER (1 << 13) +#define OTGSC_STS_DATA_PULSE (1 << 14) +/* interrupt status: (write to clear) */ +#define OTGSC_IS_MASK (0x7f << 16) +#define OTGSC_IS_USB_ID (1 << 16) +#define OTGSC_IS_A_VBUS_VALID (1 << 17) +#define OTGSC_IS_A_SESSION_VALID (1 << 18) +#define OTGSC_IS_B_SESSION_VALID (1 << 19) +#define OTGSC_IS_B_SESSION_END (1 << 20) +#define OTGSC_IS_1ms_TIMER (1 << 21) +#define OTGSC_IS_DATA_PULSE (1 << 22) +/* interrupt enables: */ +#define OTGSC_IE_MASK (0x7f << 24) +#define OTGSC_IE_USB_ID (1 << 24) +#define OTGSC_IE_A_VBUS_VALID (1 << 25) +#define OTGSC_IE_A_SESSION_VALID (1 << 26) +#define OTGSC_IE_B_SESSION_VALID (1 << 27) +#define OTGSC_IE_B_SESSION_END (1 << 28) +#define OTGSC_IE_1ms_TIMER (1 << 29) +#define OTGSC_IE_DATA_PULSE (1 << 30) + +#if 1 /* FIXME these here for compatibility between my names and Leo's */ +/* OTG interrupt enable bit masks */ +#define OTGSC_INTERRUPT_ENABLE_BITS_MASK OTGSC_IE_MASK +#define OTGSC_INTSTS_MASK OTGSC_IS_MASK + +/* OTG interrupt status bit masks */ +#define OTGSC_INTERRUPT_STATUS_BITS_MASK OTGSC_IS_MASK +#endif + +/* x_USBMODE */ +#define USBMODE_SLOM (1 << 3) /* setup lockout mode */ +#define USBMODE_ES (1 << 2) /* (big) endian select */ +#define USBMODE_CM_MASK (3 << 0) /* controller mode mask */ +#define USBMODE_CM_HOST (3 << 0) /* host */ +#define USBMODE_CM_DEVICE (2 << 0) /* device */ +#define USBMODE_CM_reserved (1 << 0) /* reserved */ + +/* USBCMD */ +#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ +#define UCMD_RESET (1 << 1) /* controller reset */ +#define UCMD_ITC_NO_THRESHOLD (~(0xff << 16)) /* Interrupt Threshold */ + +/* OTG_MIRROR */ +#define OTGM_SESEND (1 << 4) /* B device session end */ +#define OTGM_VBUSVAL (1 << 3) /* Vbus valid */ +#define OTGM_BSESVLD (1 << 2) /* B session Valid */ +#define OTGM_ASESVLD (1 << 1) /* A session Valid */ +#define OTGM_IDIDG (1 << 0) /* OTG ID pin status */ + /* 1=high: Operate as B-device */ + /* 0=low : Operate as A-device */ + +#define HCSPARAMS_PPC (0x1<<4) /* Port Power Control */ + +extern enum fsl_usb2_modes get_usb_mode(struct fsl_usb2_platform_data *pdata); +#endif diff --git a/arch/arm/plat-mxs/include/mach/bus_freq.h b/arch/arm/plat-mxs/include/mach/bus_freq.h new file mode 100644 index 000000000000..0c41cd2205ff --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/bus_freq.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef BUS_FREQ_H__ +#define BUS_FREQ_H__ + +#define VERY_HI_RATE 2000000000 +#define LCD_ON_CPU_FREQ_KHZ 261818 +#define OPERATION_WP_SUPPORTED 6 + +struct profile { + int cpu; + int ahb; + int emi; + int ss; + int vddd; + int vddd_bo; + int cur; + int vddio; + int vdda; + u16 xbus; + /* map of the upper 16 bits of HW_CLKCTRL_HBUS register */ + u16 h_autoslow_flags; +}; + +/* map of the upper 16 bits of HW_CLKCTRL_HBUS register */ +int is_hclk_autoslow_ok(void); + +extern int timing_ctrl_rams(int ss); + +#endif diff --git a/arch/arm/plat-mxs/include/mach/clkdev.h b/arch/arm/plat-mxs/include/mach/clkdev.h new file mode 100644 index 000000000000..d6a82c8d5782 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/clkdev.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +extern int __clk_get(struct clk *clk); +extern void __clk_put(struct clk *clk); + +#endif diff --git a/arch/arm/plat-mxs/include/mach/clock.h b/arch/arm/plat-mxs/include/mach/clock.h new file mode 100644 index 000000000000..b506468976b5 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/clock.h @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_CLOCK_H +#define __ASM_ARM_ARCH_CLOCK_H + +#ifndef __ASSEMBLER__ + +#include <linux/list.h> +#include <asm/clkdev.h> + +struct clk { + int id; + struct clk *parent; + struct clk *secondary; + unsigned long flags; + + int ref; + unsigned int scale_bits; + unsigned int enable_bits; + unsigned int bypass_bits; + unsigned int busy_bits; + unsigned int xtal_busy_bits; + + unsigned int wait:1; + unsigned int invert:1; + + void __iomem *enable_reg; + void __iomem *scale_reg; + void __iomem *bypass_reg; + void __iomem *busy_reg; + + /* + * Function ptr to set the clock to a new rate. The rate must match a + * supported rate returned from round_rate. Leave blank if clock is not + * programmable + */ + int (*set_rate) (struct clk *, unsigned long); + /* + * Function ptr to get the clock rate. + */ + unsigned long (*get_rate) (struct clk *); + /* + * Function ptr to round the requested clock rate to the nearest + * supported rate that is less than or equal to the requested rate. + */ + unsigned long (*round_rate) (struct clk *, unsigned long); + /* + * Function ptr to enable the clock. Leave blank if clock can not + * be gated. + */ + int (*enable) (struct clk *); + /* + * Function ptr to disable the clock. Leave blank if clock can not + * be gated. + */ + void (*disable) (struct clk *); + /* Function ptr to set the parent clock of the clock. */ + int (*set_parent) (struct clk *, struct clk *); + + /* Function ptr to change the parent clock depending + * the system configuration at that time. Will only + * change the parent clock if the ref count is 0 (the clock + * is not being used) + */ + int (*set_sys_dependent_parent) (struct clk *); + +}; + +int clk_get_usecount(struct clk *clk); +extern int clk_register(struct clk_lookup *lookup); +extern void clk_unregister(struct clk_lookup *lookup); + +bool clk_enable_h_autoslow(bool enable); +void clk_set_h_autoslow_flags(u16 mask); +void clk_en_public_h_asm_ctrl(bool (*enable_func)(bool), + void (*set_func)(u16)); + +struct mxs_emi_scaling_data { + u32 emi_div; + u32 frac_div; + u32 cur_freq; + u32 new_freq; +}; + + + +#ifdef CONFIG_MXS_RAM_FREQ_SCALING +extern int mxs_ram_freq_scale(struct mxs_emi_scaling_data *); +extern u32 mxs_ram_funcs_sz; +#else +static inline int mxs_ram_freq_scale(struct mxs_emi_scaling_data *p) +{ +} +static u32 mxs_ram_funcs_sz; +#endif + +/* Clock flags */ +/* 0 ~ 16 attribute flags */ +#define ALWAYS_ENABLED (1 << 0) /* Clock cannot be disabled */ +#define RATE_FIXED (1 << 1) /* Fixed clock rate */ +#define CPU_FREQ_TRIG_UPDATE (1 << 2) /* CPUFREQ trig update */ + +/* 16 ~ 23 reservied */ +/* 24 ~ 31 run time flags */ + +#define CLK_REF_UNIT 0x00010000 +#define CLK_REF_LIMIT 0xFFFF0000 +#define CLK_EN_MASK 0x0000FFFF +#endif /* __ASSEMBLER__ */ + +#endif diff --git a/arch/arm/plat-mxs/include/mach/ddi_bc.h b/arch/arm/plat-mxs/include/mach/ddi_bc.h new file mode 100644 index 000000000000..21ca9217cdaa --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/ddi_bc.h @@ -0,0 +1,715 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _DDI_BC_H +#define _DDI_BC_H + +#include <linux/types.h> + +#define DDI_BC_MAX_RESTART_CYCLES 100 + +#define DDI_BC_LIION_CHARGING_VOLTAGE 4200 +#define DDI_BC_ALKALINE_NIMH_CHARGING_VOLTAGE 1750 + +/* brief Defines battery charger states. */ +typedef enum _ddi_bc_State { + /* brief TBD */ + DDI_BC_STATE_UNINITIALIZED = 0, + /* brief TBD */ + DDI_BC_STATE_BROKEN = 1, + /* brief TBD */ + DDI_BC_STATE_DISABLED = 2, + /* brief TBD */ + DDI_BC_STATE_WAITING_TO_CHARGE = 3, + /* brief TBD */ + DDI_BC_STATE_CONDITIONING = 4, + /* brief TBD */ + DDI_BC_STATE_CHARGING = 5, + /* brief TBD */ + DDI_BC_STATE_TOPPING_OFF = 6, + /* brief TBD */ + DDI_BC_STATE_DCDC_MODE_WAITING_TO_CHARGE = 7, + +} ddi_bc_State_t; + +typedef enum _ddi_bc_BrokenReason { + /* brief TBD */ + DDI_BC_BROKEN_UNINITIALIZED = 0, + /* brief TBD */ + DDI_BC_BROKEN_CHARGING_TIMEOUT = 1, + /* brief TBD */ + DDI_BC_BROKEN_FORCED_BY_APPLICATION = 2, + /* brief TBD */ + DDI_BC_BROKEN_EXTERNAL_BATTERY_VOLTAGE_DETECTED = 3, + /* brief TBD */ + DDI_BC_BROKEN_NO_BATTERY_DETECTED = 4, + +} ddi_bc_BrokenReason_t; + +/* brief Defines the battery charger configuration. */ +typedef struct _ddi_bc_Cfg { + /* brief Units in milliseconds. */ + /* */ + /* This field configures the expected period between calls to */ + /* ddi_bc_StateMachine. If die temperature monitoring is */ + /* enabled, then the data sheet recommends the period be around */ + /* 100ms or less. */ + /* */ + /* Note that this period defines the minimum time resolution of */ + /* the battery charger. */ + + uint32_t u32StateMachinePeriod; + + /* brief Units in mA/s. */ + /* */ + /* This field configures the slope of the current ramp. Any */ + /* time the battery charger increases its current draw, it will */ + /* ramp up the current no faster than this rate. */ + /* */ + /* Note that the minimum time resolution of the battery charger */ + /* is the configured period between calls to advance the state */ + /* machine. Also, the hardware has a minimum current resolution */ + /* of 10mA. If the given ramp slope cannot be expressed */ + /* exactly, then the largest expressible smaller slope will be */ + /* the result. If the actual period between calls to */ + /* ddi_bc_StateMachine is irregular, the current may ramp faster */ + /* than indicated. */ + + uint16_t u16CurrentRampSlope; + + /* brief Units in millivolts. */ + /* */ + /* This field configures the threshold conditioning voltage. If */ + /* the battery's voltage is below this value, it will be */ + /* conditioned until its voltage rises above the maximum */ + /* conditioning voltage. After that, the battery will be */ + /* charged normally. */ + /* */ + /* Note that the hardware has a minimum resolution of 8mV. If */ + /* the given voltage cannot be expressed exactly, then the */ + /* smallest expressible larger value will be used. */ + + uint16_t u16ConditioningThresholdVoltage; + + /* brief Units in millivolts. */ + /* */ + /* This field configures the maximum conditioning voltage. If */ + /* the battery charger is conditioning a battery, normal */ + /* charging begins when the voltage rises above this value. */ + /* */ + /* This value should be slightly higher than the threshold */ + /* conditioning voltage because it is measured while a */ + /* conditioning current is actually flowing to the battery. */ + /* With a conditioning current of 0.1C, reasonable values for */ + /* the threshold and maximum conditioning voltages are 2.9V */ + /* and 3.0V respectively. */ + /* */ + /* Note that the hardware has a minimum resolution of 8mV. If */ + /* the given voltage cannot be expressed exactly, then the */ + /* smallest expressible larger value will be used. */ + + uint16_t u16ConditioningMaxVoltage; + + /* brief Units in milliamps. */ + /* */ + /* This field configures the maximum conditioning current. */ + /* This is the maximum current that will be offered to a */ + /* battery while it is being conditioned. A typical value is */ + /* 0.1C. */ + /* */ + /* Note that the hardware has a minimum resolution of 10mA */ + /* (see the data sheet for details). If the given current */ + /* cannot be expressed exactly, then the largest expressible */ + /* smaller value will be used. */ + + uint16_t u16ConditioningCurrent; + + /* brief Units in milliseconds. */ + /* */ + /* This field configures the conditioning time-out. This is */ + /* the maximum amount of time that a battery will be */ + /* conditioned before the battery charger declares it to be */ + /* broken. */ + /* */ + /* Note that the minimum time resolution of the battery */ + /* charger is the configured period between calls to advance */ + /* the state machine. If the given time-out cannot be */ + /* expressed exactly, then the shortest expressible longer */ + /* value will be used. */ + + uint32_t u32ConditioningTimeout; + + /* brief Units in millivolts. */ + /* */ + /* This field configures the final charging voltage. At this */ + /* writing, only two values are permitted: 4100 or 4200. */ + + uint16_t u16ChargingVoltage; + + /* brief Units in milliamps. */ + /* */ + /* This field configures the maximum current offered to a */ + /* charging battery. */ + /* */ + /* Note that the hardware has a minimum resolution of 10mA */ + /* (see the data sheet for details). If the given current */ + /* cannot be expressed exactly, then the largest expressible */ + /* smaller value will be used. */ + + uint16_t u16ChargingCurrent; + + /* brief Units in milliamps. */ + /* */ + /* This field configures the current flow below which a */ + /* charging battery is regarded as fully charged (typical */ + /* 0.1C). At this point, the battery will be topped off. */ + /* */ + /* Note that the hardware has a minimum resolution of 10mA */ + /* (see the data sheet for details). If the given current */ + /* cannot be expressed exactly, then the largest expressible */ + /* smaller value will be used. */ + + uint16_t u16ChargingThresholdCurrent; + + /* brief Units in milliamps. */ + /* */ + /* When charging while the DCDC converter's are enabled, the charger */ + /* is suppling current to both the battery and the Vbat input of the */ + /* DCDC converter. Once the total battery charger current falls */ + /* below this level, the charger will then stop charging until the */ + /* the battery voltage reaches the BC_LOW_DCDCMODE_BATTERY_VOLTAGE */ + /* threshold or until the DCDCs are no longer enabled. */ + /* */ + /* Typically, this value should be left at 180 to avoid the risk */ + /* of topping off the battery too long in DCDC mode and avoid */ + /* exceeding the BC_CHARGING_TIMEOUT time which would put the charger */ + /* driver in the broken state and completely disable charging. */ + /* */ + /* Note that the hardware has a minimum resolution of 10mA */ + /* (see the data sheet for details). If the given current */ + /* cannot be expressed exactly, then the largest expressible */ + /* smaller value will be used. */ + uint16_t u16DdcdModeChargingThresholdCurrent; + + /* brief Units in milliseconds. */ + /* */ + /* This field configures the charging time-out. This is the */ + /* maximum amount of time that a battery will be charged */ + /* before the battery charger declares it to be broken. */ + /* */ + /* Note that the minimum time resolution of the battery */ + /* charger is the configured period between calls to advance */ + /* the state machine. If the given time-out cannot be */ + /* expressed exactly, then the shortest expressible longer */ + /* value will be used. */ + + uint32_t u32ChargingTimeout; + + /* brief Units in milliseconds. */ + /* */ + /* This field configures the top-off period. This is the */ + /* amount of time a battery will be held in the Topping Off */ + /* state before it is declared fully charged. */ + /* */ + /* Note that the minimum time resolution of the battery */ + /* charger is the configured period between calls to advance */ + /* the state machine. If the given time-out cannot be */ + /* expressed exactly, then the shortest expressible longer */ + /* value will be used. */ + + uint32_t u32TopOffPeriod; + + /* brief Units in milliseconds. */ + /* */ + /* This field configures the top-off period when the DCDC */ + /* converters are enabled. To avoid topping off the LiIon */ + /* battery too long and reducing it's long term capacity, */ + /* This time should be kept failry short. */ + /* */ + /* Note that the minimum time resolution of the battery */ + /* charger is the configured period between calls to advance */ + /* the state machine. If the given time-out cannot be */ + /* expressed exactly, then the shortest expressible longer */ + /* value will be used. */ + uint32_t u32DcdcModeTopOffPeriod; + + /* brief Causes the battery charger to use an externally generated bias current */ + /* */ + /* If cleared, this causes the battery charger to use an */ + /* externally generated bias current, which is expected to be */ + /* quite precise. Otherwise, the battery charger will */ + /* generate a lesser-quality bias current internally. */ + + uint8_t useInternalBias:1; + + /* brief Indicates that the battery charger is to monitor the die temperature. */ + /* */ + /* If set, this field indicates that the battery charger is to */ + /* monitor the die temperature. See below for fields that */ + /* configure the details. */ + + uint8_t monitorDieTemp:1; + + /* brief Indicates that the battery charger is to monitor the battery temperature. */ + /* */ + /* If set, this field indicates that the battery charger is to */ + /* monitor the battery temperature. See below for fields that */ + /* configure the details. */ + + uint8_t monitorBatteryTemp:1; + + /* brief Units in degrees centigrade. */ + /* */ + /* Note that the hardware reports die temperature in ranges of */ + /* 10 degree resolution minimum (see the data sheet for */ + /* details). If the battery charger is monitoring the die */ + /* temperature, and it rises to a range that includes a */ + /* temperature greater than or equal to this value, the */ + /* charging current will be clamped to the safe current. */ + + int8_t u8DieTempHigh; + + /* brief Units in degrees centigrade. */ + /* */ + /* Note that the hardware reports die temperature in ranges of */ + /* 10 degrees minimum (see the data sheet for details). If the */ + /* charging current is being clamped because of a high die */ + /* temperature, and it falls to a range that doesn't include a */ + /* temperatures greater than or equal to this value, the */ + /* charging current clamp will be released. */ + + int8_t u8DieTempLow; + + /* brief Units in milliamps. */ + /* */ + /* If the battery charger detects a high die temperature, it */ + /* will clamp the charging current at or below this value. */ + + uint16_t u16DieTempSafeCurrent; + + /* brief If the battery charger is monitoring the battery */ + /* temperature, this field indicates the LRADC channel to */ + /* read. */ + + uint8_t u8BatteryTempChannel; + + /* brief If the battery charger is monitoring the battery */ + /* temperature, and it rises to a measurement greater than or */ + /* equal to this value, the charging current will be clamped */ + /* to the corresponding safe current. */ + + uint16_t u16BatteryTempHigh; + + /* brief If the charging current is being clamped because of a high */ + /* battery temperature, and it falls below this value, the */ + /* charging current clamp will be released. */ + + uint16_t u16BatteryTempLow; + + /* brief Units in milliamps. */ + /* */ + /* If the battery charger detects a high battery temperature, */ + /* it will clamp the charging current at or below this value. */ + + uint16_t u16BatteryTempSafeCurrent; + + /* brief Units in millivolts. */ + /* */ + /* In the WaitingToCharge state, if we are in DCDC */ + /* operating modes, if the battery voltage measurement */ + /* is below this value, we immediately proceed with charging. */ + /* the low criteria for this value is that it must be high */ + /* to not risk the battery voltage getting too low. The */ + /* upper criteria is that you do not want the IR voltage */ + /* drop under heavy loads to make you start charging too soon */ + /* because the goal in DCDC operating mode is to not be constantly */ + /* topping off the battery which can shorten its life */ + + uint16_t u16LowDcdcBatteryVoltage_mv; + + uint32_t u32StateMachineNonChargingPeriod; +} ddi_bc_Cfg_t; + +/* Status returned by Battery Charger functions. */ + +typedef enum _ddi_bc_Status { + /* brief TBD */ + DDI_BC_STATUS_SUCCESS = 0, + /* brief TBD */ + DDI_BC_STATUS_HARDWARE_DISABLED, + /* brief TBD */ + DDI_BC_STATUS_BAD_BATTERY_MODE, + /* brief TBD */ + DDI_BC_STATUS_CLOCK_GATE_CLOSED, + /* brief TBD */ + DDI_BC_STATUS_NOT_INITIALIZED, + /* brief TBD */ + DDI_BC_STATUS_ALREADY_INITIALIZED, + /* brief TBD */ + DDI_BC_STATUS_BROKEN, + /* brief TBD */ + DDI_BC_STATUS_NOT_BROKEN, + /* brief TBD */ + DDI_BC_STATUS_NOT_DISABLED, + /* brief TBD */ + DDI_BC_STATUS_BAD_ARGUMENT, + /* brief TBD */ + DDI_BC_STATUS_CFG_BAD_BATTERY_TEMP_CHANNEL, + /* brief TBD */ + DDI_BC_STATUS_CFG_BAD_CHARGING_VOLTAGE, +} ddi_bc_Status_t; + + +/* BCM Event Codes */ + +/* These are the codes that might be published to PMI Subscribers. */ + + +#define DDI_BC_EVENT_GROUP (11<<10) + +/* brief TBD */ +/* todo [PUBS] Add definition(s)... */ +typedef enum { + /* Use the error code group value to make events unique for the EOI */ + /* brief TBD */ + ddi_bc_MinEventCode = DDI_BC_EVENT_GROUP, + /* brief TBD */ + ddi_bc_WaitingToChargeCode, + /* brief TBD */ + ddi_bc_State_ConditioningCode, + /* brief TBD */ + ddi_bc_State_Topping_OffCode, + /* brief TBD */ + ddi_bc_State_BrokenCode, + /* brief TBD */ + ddi_bc_SettingChargeCode, + /* brief TBD */ + ddi_bc_RaisingDieTempAlarmCode, + /* brief TBD */ + ddi_bc_DroppingDieTempAlarmCode, + + /* brief TBD */ + ddi_bc_MaxEventCode, + /* brief TBD */ + ddi_bc_DcdcModeWaitingToChargeCode +} ddi_bc_Event_t; + + +/* Prototypes */ + + + +/* brief Initialize the Battery Charger. */ +/* */ +/* fntype Function */ +/* */ +/* This function initializes the Battery Charger. */ +/* */ +/* param[in] pCfg A pointer to the new configuration. */ +/* */ +/* retval DDI_BC_STATUS_SUCCESS */ +/* If the operation succeeded. */ +/* retval DDI_BC_STATUS_ALREADY_INITIALIZED */ +/* If the Battery Charger is already initialized. */ +/* retval DDI_BC_STATUS_HARDWARE_DISABLED */ +/* If the Battery Charger hardware is disabled by a laser fuse. */ +/* retval DDI_BC_STATUS_BAD_BATTERY_MODE */ +/* If the power supply is set up for a non-rechargeable battery. */ +/* retval DDI_BC_STATUS_CLOCK_GATE_CLOSED */ +/* If the clock gate for the power supply registers is closed. */ +/* retval DDI_BC_STATUS_CFG_BAD_CHARGING_VOLTAGE */ +/* If the charging voltage is not either 4100 or 4200. */ +/* retval DDI_BC_STATUS_CFG_BAD_BATTERY_TEMP_CHANNEL */ +/* If the LRADC channel number for monitoring battery temperature */ +/* is bad. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_init.c. */ + +extern ddi_bc_Status_t ddi_bc_Init(ddi_bc_Cfg_t *pCfg); + +/* */ +/* brief Report the Battery Charger configuration. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the Battery Charger configuration. */ +/* */ +/* Note that, if the Battery Charger has not yet been initialized, the data */ +/* returned by this function is unknown. */ +/* */ +/* param[in,out] pCfg A pointer to a structure that will receive the data. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern void ddi_bc_QueryCfg(ddi_bc_Cfg_t *pCfg); + +/* */ +/* brief Shut down the Battery Charger. */ +/* */ +/* fntype Function */ +/* */ +/* This function immediately shuts down the Battery Charger hardware and */ +/* returns the state machine to the Uninitialized state. Use this function to */ +/* safely mummify the battery charger before retiring it from memory. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern void ddi_bc_ShutDown(void); + +/* */ +/* brief Advances the state machine. */ +/* */ +/* fntype Function */ +/* */ +/* This function advances the state machine. */ +/* */ +/* retval DDI_BC_STATUS_SUCCESS If all goes well */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* retval DDI_BC_STATUS_BROKEN If the battery violated a time-out */ +/* and has been declared broken. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern ddi_bc_Status_t ddi_bc_StateMachine(void); + +/* */ +/* brief Get the Battery Charger's current state. */ +/* */ +/* fntype Function */ +/* */ +/* This function returns the current state. */ +/* */ +/* retval The current state. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern ddi_bc_State_t ddi_bc_GetState(void); + +/* */ +/* brief Disable the Battery Charger. */ +/* */ +/* fntype Function */ +/* */ +/* This function forces the Battery Charger into the Disabled state. */ +/* */ +/* retval DDI_BC_STATUS_SUCCESS If all goes well */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern ddi_bc_Status_t ddi_bc_SetDisable(void); + +/* */ +/* brief Enable the Battery Charger. */ +/* */ +/* fntype Function */ +/* */ +/* If the Battery Charger is in the Disabled state, this function moves it to */ +/* the Waiting to Charge state. */ +/* */ +/* retval DDI_BC_STATUS_SUCCESS If all goes well */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* retval DDI_BC_STATUS_NOT_DISABLED If the Battery Charger is not */ +/* disabled. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern ddi_bc_Status_t ddi_bc_SetEnable(void); + +/* */ +/* brief Declare the battery to be broken. */ +/* */ +/* fntype Function */ +/* */ +/* This function forces the Battery Charger into the Broken state. */ +/* */ +/* retval DDI_BC_STATUS_SUCCESS If all goes well */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern ddi_bc_Status_t ddi_bc_SetBroken(void); + +/* */ +/* brief Declare the battery to be fixed. */ +/* */ +/* fntype Function */ +/* */ +/* If the Battery Charger is in the Broken state, this function moves it to */ +/* the Disabled state. */ +/* */ +/* retval DDI_BC_STATUS_SUCCESS If all goes well */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* retval DDI_BC_STATUS_NOT_BROKEN If the Battery Charger is not broken. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern ddi_bc_Status_t ddi_bc_SetFixed(void); + +/* */ +/* brief Set the current limit. */ +/* */ +/* fntype Function */ +/* */ +/* This function applies a limit to the current that the Battery Charger can */ +/* draw. */ +/* */ +/* param[in] u16Limit The maximum current the Battery Charger can draw */ +/* (in mA). */ +/* */ +/* retval The expressible version of the limit. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern uint16_t ddi_bc_SetCurrentLimit(uint16_t u16Limit); + + +/* */ +/* brief Report the current limit. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the limit to the current that the Battery Charger can */ +/* draw. */ +/* */ +/* retval The current limit. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern uint16_t ddi_bc_GetCurrentLimit(void); + + +/* */ +/* brief Set the current threshold. */ +/* */ +/* fntype Function */ +/* */ +/* */ +/* param[in] u16Current Current threshold where charger deactivates (in mA). */ +/* */ +/* */ + +extern uint16_t ddi_bc_SetCurrentThreshold(uint16_t u16Current); + + +/* */ +/* brief Set the battery charger state machine period. */ +/* */ +/* fntype Function */ +/* */ +/* This function sets a new state machine period. The Period and Slope should */ +/* be coordinated to achieve the minimal ramp step current which will minimize */ +/* transients on the system. */ +/* */ +/* param[in] u32StateMachinePeriod (in milliseconds) */ +/* param[in] u16CurrentRampSlope (in mA/s) */ +/* */ +/* retval SUCCESS If all goes well */ +/* retval ERROR_DDI_BCM_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* */ + +extern ddi_bc_Status_t ddi_bc_SetNewPeriodAndSlope(uint32_t + u32StateMachinePeriod, + uint16_t + u16CurrentRampSlope); + + +/* */ +/* brief Report the state machine period. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the battery charger period. */ +/* */ +/* retval The battery charger period (in milliseconds). */ +/* */ + +extern uint32_t ddi_bc_GetStateMachinePeriod(void); + + +/* */ +/* brief Report the current ramp slope. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the current ramp slope. */ +/* */ +/* retval The current ramp slope (in mA/s). */ +/* */ + +extern uint32_t ddi_bc_GetCurrentRampSlope(void); + + +/* */ +/* brief Report the time spent in the present state (milliseconds) */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the time spent in the present charging state. Note that */ +/* for the states that actually charge the battery, this time does not include the */ +/* time spent under alarm conditions such as die termperature alarm or battery */ +/* temperature alarm. */ +/* */ +/* retval The time spent in the current state in milliseconds. */ +/* */ + +uint32_t ddi_bc_GetStateTime(void); + + +/* */ +/* brief Report the reason for being in the broken state */ +/* */ +/* fntype Function */ +/* */ +/* */ +/* retval ddi_bc_BrokenReason_t enumeration */ +/* */ + +ddi_bc_BrokenReason_t ddi_bc_GetBrokenReason(void); + + +/* */ +/* brief Restart the charge cycle */ +/* */ +/* fntype Function */ +/* */ +/* retval SUCCESS */ +/* */ + +ddi_bc_Status_t ddi_bc_ForceChargingToStart(void); + +void fsl_enable_usb_plugindetect(void); + +int fsl_is_usb_plugged(void); + +/* End of file */ + +#endif /* _DDI_BC_H */ +/* @} */ diff --git a/arch/arm/plat-mxs/include/mach/debug-macro.S b/arch/arm/plat-mxs/include/mach/debug-macro.S new file mode 100644 index 000000000000..147cda360cb3 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/debug-macro.S @@ -0,0 +1,42 @@ +/* + * Debugging macro include header + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <mach/hardware.h> + + .macro addruart,rx,tmp + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =MXS_LL_UART_PADDR @ physical + ldrne \rx, =MXS_LL_UART_VADDR @ virtual + .endm + + .macro senduart,rd,rx + strb \rd, [\rx, #0] @ data register at 0 + .endm + + .macro waituart,rd,rx +1001: ldr \rd, [\rx, #0x18] @ UARTFLG + tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full + bne 1001b + .endm + + .macro busyuart,rd,rx +1001: ldr \rd, [\rx, #0x18] @ UARTFLG + tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy + bne 1001b + .endm diff --git a/arch/arm/plat-mxs/include/mach/device.h b/arch/arm/plat-mxs/include/mach/device.h new file mode 100644 index 000000000000..080add7d8fa2 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/device.h @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_DEVICE_H +#define __ASM_ARM_ARCH_DEVICE_H + +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <linux/leds.h> + +#include <asm/mach/time.h> + +#define MXS_MAX_DEVICES 128 + +struct mxs_sys_timer { + struct sys_timer timer; + unsigned char id; + unsigned char clk_sel; + unsigned char resv[2]; + int irq; + struct clk *clk; + void __iomem *base; +}; + +struct mxs_dev_lookup { + char *name; + unsigned long lock; + int size; + struct platform_device *pdev; +}; + +/* Define the Platform special structure for each device type*/ +struct mxs_dma_plat_data { + unsigned int burst8:1; + unsigned int burst:1; + unsigned int chan_base; + unsigned int chan_num; +}; + +struct fsl_otp_data { + char **fuse_name; + char *regulator_name; + unsigned int fuse_num; +}; + +struct mxs_i2c_plat_data { + unsigned int pioqueue_mode:1; +}; + +struct mxs_lradc_plat_data { + unsigned int vddio_voltage; + unsigned int battery_voltage; +}; + +struct mxskbd_keypair { + int raw; + int kcode; +}; + +struct mxs_kbd_plat_data { + struct mxskbd_keypair *keypair; + int channel; + unsigned int btn_enable; /* detect enable bits */ + unsigned int btn_irq_stat; /* detect irq status bits */ + unsigned int btn_irq_ctrl; /* detect irq enable bits */ +}; + +struct mxs_touchscreen_plat_data { + u8 x_plus_chan; + u8 x_minus_chan; + u8 y_plus_chan; + u8 y_minus_chan; + unsigned int x_plus_val; + unsigned int x_minus_val; + unsigned int y_plus_val; + unsigned int y_minus_val; + unsigned int x_plus_mask; + unsigned int x_minus_mask; + unsigned int y_plus_mask; + unsigned int y_minus_mask; +}; + +struct mxs_auart_plat_data { + unsigned int fifo_size:6; + unsigned int dma_mode:1; + unsigned int timeout; + unsigned int dma_rx_buffer_size; + const char *clk; +}; + +struct mxs_pwm_led { + struct led_classdev dev; + const char *name; + unsigned int pwm; +}; + +struct mxs_pwm_leds_plat_data { + unsigned int num; + struct mxs_pwm_led *leds; +}; + +struct mxs_mma7450_platform_data { + char *reg_dvdd_io; + char *reg_avdd; + void (*gpio_pin_get) (void); + void (*gpio_pin_put) (void); + int int1; + int int2; +}; + +struct mxs_spi_platform_data { + int (*hw_pin_init)(void); + int (*hw_pin_release)(void); + + char *clk; +}; + +struct mxs_audio_platform_data { + int intr_id_hp; + int ext_ram; + struct clk *saif_mclock; + + int hp_irq; + int (*hp_status) (void); + + int sysclk; + + int (*init) (void); /* board specific init */ + int (*amp_enable) (int enable); + int (*finit) (void); /* board specific finit */ + void *priv; /* used by board specific functions */ +}; + +struct mxs_persistent_bit_config { + int reg; + int start; + int width; + const char *name; +}; + +struct mxs_platform_persistent_data { + const struct mxs_persistent_bit_config *bit_config_tab; + int bit_config_cnt; +}; + +extern void mxs_timer_init(struct mxs_sys_timer *timer); +extern void mxs_nomatch_timer_init(struct mxs_sys_timer *timer); + +extern void mxs_nop_release(struct device *dev); +extern int mxs_add_devices(struct platform_device *, int num, int level); +extern int mxs_add_device(struct platform_device *, int level); +extern struct platform_device *mxs_get_device(char *name, int id); +extern struct mxs_dev_lookup *mxs_get_devices(char *name); + +extern int iram_init(unsigned long base, unsigned long size); + +/* mxs ssp sd/mmc data definitons */ +struct mxs_mmc_platform_data { + int (*hw_init)(void); + void (*hw_release)(void); + void (*cmd_pullup)(int enable); + int (*get_wp)(void); + unsigned long (*setclock)(unsigned long hz); + unsigned int caps; + unsigned int min_clk; + unsigned int max_clk; + int read_uA; + int write_uA; + char *power_mmc; + char *clock_mmc; +}; +/* end of mxs ssp sd/mmc data definitions */ + +#ifdef CONFIG_MXS_ICOLL +extern void __init avic_init_irq(void __iomem *base, int nr_irqs); +#endif + +#endif diff --git a/arch/arm/plat-mxs/include/mach/dmaengine.h b/arch/arm/plat-mxs/include/mach/dmaengine.h new file mode 100644 index 000000000000..1600d9762a9e --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/dmaengine.h @@ -0,0 +1,518 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_DMA_H +#define __ASM_ARM_ARCH_DMA_H + +#ifndef ARCH_DMA_PIO_WORDS +#define DMA_PIO_WORDS 15 +#else +#define DMA_PIO_WORDS ARCH_DMA_PIO_WORDS +#endif + +#define MXS_DMA_ALIGNMENT 8 + +/** + * struct mxs_dma_cmd_bits - MXS DMA hardware command bits. + * + * This structure describes the in-memory layout of the command bits in a DMA + * command. See the appropriate reference manual for a detailed description + * of what these bits mean to the DMA hardware. + */ +struct mxs_dma_cmd_bits { + unsigned int command:2; +#define NO_DMA_XFER 0x00 +#define DMA_WRITE 0x01 +#define DMA_READ 0x02 +#define DMA_SENSE 0x03 + + unsigned int chain:1; + unsigned int irq:1; + unsigned int nand_lock:1; + unsigned int nand_wait_4_ready:1; + unsigned int dec_sem:1; + unsigned int wait4end:1; + unsigned int halt_on_terminate:1; + unsigned int terminate_flush:1; + unsigned int resv2:2; + unsigned int pio_words:4; + unsigned int bytes:16; +}; + +/* fill the word 1 of the DMA channel command structure */ +#define fill_dma_word1(cmdp, _cmd, _chain, _irq, _lock, _wait_ready, _dec_sem,\ + _wait4end, _halt_on_term, _term_flush, _pio_words, _bytes)\ + do { \ + struct mxs_dma_cmd_bits *bits = &(cmdp)->bits; \ + \ + /* reset all the fields first */ \ + (cmdp)->data = 0; \ + \ + bits->command = _cmd; \ + bits->chain = _chain; \ + bits->irq = _irq; \ + bits->nand_lock = _lock; \ + bits->nand_wait_4_ready = _wait_ready; \ + bits->dec_sem = _dec_sem; \ + bits->wait4end = _wait4end; \ + bits->halt_on_terminate = _halt_on_term; \ + bits->terminate_flush = _term_flush; \ + bits->pio_words = _pio_words; \ + bits->bytes = _bytes; \ + } while (0) + +/** + * struct mxs_dma_cmd - MXS DMA hardware command. + * + * This structure describes the in-memory layout of an entire DMA command, + * including space for the maximum number of PIO accesses. See the appropriate + * reference manual for a detailed description of what these fields mean to the + * DMA hardware. + */ +struct mxs_dma_cmd { + unsigned long next; + union { + unsigned long data; + struct mxs_dma_cmd_bits bits; + } cmd; + union { + dma_addr_t address; + unsigned long alternate; + }; + unsigned long pio_words[DMA_PIO_WORDS]; +}; + +/** + * struct mxs_dma_desc - MXS DMA command descriptor. + * + * This structure incorporates an MXS DMA hardware command structure, along + * with metadata. + * + * @cmd: The MXS DMA hardware command block. + * @flags: Flags that represent the state of this DMA descriptor. + * @address: The physical address of this descriptor. + * @buffer: A convenient place for software to put the virtual address of the + * associated data buffer (the physical address of the buffer + * appears in the DMA command). The MXS platform DMA software doesn't + * use this field -- it is provided as a convenience. + * @node: Links this structure into a list. + */ +struct mxs_dma_desc { + struct mxs_dma_cmd cmd; + unsigned int flags; +#define MXS_DMA_DESC_READY 0x80000000 +#define MXS_DMA_DESC_FIRST 0x00000001 +#define MXS_DMA_DESC_LAST 0x00000002 + dma_addr_t address; + void *buffer; + struct list_head node; +}; + +struct mxs_dma_info { + unsigned int status; +#define MXS_DMA_INFO_ERR 0x00000001 +#define MXS_DMA_INFO_ERR_STAT 0x00010000 + unsigned int buf_addr; + unsigned int xfer_count; +}; + +/** + * struct mxs_dma_chan - MXS DMA channel + * + * This structure represents a single DMA channel. The MXS platform code + * maintains an array of these structures to represent every DMA channel in the + * system (see mxs_dma_channels). + * + * @name: A human-readable string that describes how this channel is + * being used or what software "owns" it. This field is set when + * when the channel is reserved by mxs_dma_request(). + * @dev: A pointer to a struct device *, cast to an unsigned long, and + * representing the software that "owns" the channel. This field + * is set when when the channel is reserved by mxs_dma_request(). + * @lock: Arbitrates access to this channel. + * @dma: A pointer to a struct mxs_dma_device representing the driver + * code that operates this channel. + * @flags: Flag bits that represent the state of this channel. + * @active_num: If the channel is not busy, this value is zero. If the channel + * is busy, this field contains the number of DMA command + * descriptors at the head of the active list that the hardware + * has been told to process. This value is set at the moment the + * channel is enabled by mxs_dma_enable(). More descriptors may + * arrive after the channel is enabled, so the number of + * descriptors on the active list may be greater than this value. + * In fact, it should always be active_num + pending_num. + * @pending_num: The number of DMA command descriptors at the tail of the + * active list that the hardware has not been told to process. + * @active: The list of DMA command descriptors either currently being + * processed by the hardware or waiting to be processed. + * Descriptors being processed appear at the head of the list, + * while pending descriptors appear at the tail. The total number + * should always be active_num + pending_num. + * @done: The list of DMA command descriptors that have either been + * processed by the DMA hardware or aborted by a call to + * mxs_dma_disable(). + */ +struct mxs_dma_chan { + const char *name; + unsigned long dev; + spinlock_t lock; + struct mxs_dma_device *dma; + unsigned int flags; +#define MXS_DMA_FLAGS_IDLE 0x00000000 +#define MXS_DMA_FLAGS_BUSY 0x00000001 +#define MXS_DMA_FLAGS_FREE 0x00000000 +#define MXS_DMA_FLAGS_ALLOCATED 0x00010000 +#define MXS_DMA_FLAGS_VALID 0x80000000 + unsigned int active_num; + unsigned int pending_num; + struct list_head active; + struct list_head done; +}; + +/** + * struct mxs_dma_device - DMA channel driver interface. + * + * This structure represents the driver that operates a DMA channel. Every + * struct mxs_dma_chan contains a pointer to a structure of this type, which is + * installed when the driver registers to "own" the channel (see + * mxs_dma_device_register()). + */ +struct mxs_dma_device { + struct list_head node; + const char *name; + void __iomem *base; + unsigned int chan_base; + unsigned int chan_num; + unsigned int data; + struct platform_device *pdev; + + /* operations */ + int (*enable) (struct mxs_dma_chan *, unsigned int); + void (*disable) (struct mxs_dma_chan *, unsigned int); + void (*reset) (struct mxs_dma_device *, unsigned int); + void (*freeze) (struct mxs_dma_device *, unsigned int); + void (*unfreeze) (struct mxs_dma_device *, unsigned int); + int (*read_semaphore) (struct mxs_dma_device *, unsigned int); + void (*add_semaphore) (struct mxs_dma_device *, unsigned int, unsigned); + void (*info)(struct mxs_dma_device *, + unsigned int, struct mxs_dma_info *info); + void (*enable_irq) (struct mxs_dma_device *, unsigned int, int); + int (*irq_is_pending) (struct mxs_dma_device *, unsigned int); + void (*ack_irq) (struct mxs_dma_device *, unsigned int); + + void (*set_target) (struct mxs_dma_device *, unsigned int, int); +}; + +/** + * mxs_dma_device_register - Register a DMA driver. + * + * This function registers a driver for a contiguous group of DMA channels (the + * ordering of DMA channels is specified by the globally unique DMA channel + * numbers given in mach/dma.h). + * + * @pdev: A pointer to a structure that represents the driver. This structure + * contains fields that specify the first DMA channel number and the + * number of channels. + */ +extern int mxs_dma_device_register(struct mxs_dma_device *pdev); + +/** + * mxs_dma_request - Request to reserve a DMA channel. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @dev: A pointer to a struct device representing the channel "owner." + * @name: A human-readable string that identifies the channel owner or the + * purpose of the channel. + */ +extern int mxs_dma_request(int channel, struct device *dev, const char *name); + +/** + * mxs_dma_release - Release a DMA channel. + * + * This function releases a DMA channel from its current owner. + * + * The channel will NOT be released if it's marked "busy" (see + * mxs_dma_enable()). + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @dev: A pointer to a struct device representing the channel "owner." If + * this doesn't match the owner given to mxs_dma_request(), the + * channel will NOT be released. + */ +extern void mxs_dma_release(int channel, struct device *dev); + +/** + * mxs_dma_enable - Enable a DMA channel. + * + * If the given channel has any DMA descriptors on its active list, this + * function causes the DMA hardware to begin processing them. + * + * This function marks the DMA channel as "busy," whether or not there are any + * descriptors to process. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern int mxs_dma_enable(int channel); + +/** + * mxs_dma_disable - Disable a DMA channel. + * + * This function shuts down a DMA channel and marks it as "not busy." Any + * descriptors on the active list are immediately moved to the head of the + * "done" list, whether or not they have actually been processed by the + * hardware. The "ready" flags of these descriptors are NOT cleared, so they + * still appear to be active. + * + * This function immediately shuts down a DMA channel's hardware, aborting any + * I/O that may be in progress, potentially leaving I/O hardware in an undefined + * state. It is unwise to call this function if there is ANY chance the hardware + * is still processing a command. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_disable(int channel); + +/** + * mxs_dma_reset - Resets the DMA channel hardware. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_reset(int channel); + +/** + * mxs_dma_freeze - Freeze a DMA channel. + * + * This function causes the channel to continuously fail arbitration for bus + * access, which halts all forward progress without losing any state. A call to + * mxs_dma_unfreeze() will cause the channel to continue its current operation + * with no ill effect. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_freeze(int channel); + +/** + * mxs_dma_unfreeze - Unfreeze a DMA channel. + * + * This function reverses the effect of mxs_dma_freeze(), enabling the DMA + * channel to continue from where it was frozen. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ + +extern void mxs_dma_unfreeze(int channel); + +/* get dma channel information */ +extern int mxs_dma_get_info(int channel, struct mxs_dma_info *info); + +/** + * mxs_dma_cooked - Clean up processed DMA descriptors. + * + * This function removes processed DMA descriptors from the "active" list. Pass + * in a non-NULL list head to get the descriptors moved to your list. Pass NULL + * to get the descriptors moved to the channel's "done" list. Descriptors on + * the "done" list can be retrieved with mxs_dma_get_cooked(). + * + * This function marks the DMA channel as "not busy" if no unprocessed + * descriptors remain on the "active" list. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @head: If this is not NULL, it is the list to which the processed + * descriptors should be moved. If this list is NULL, the descriptors + * will be moved to the "done" list. + */ +extern int mxs_dma_cooked(int channel, struct list_head *head); + +/** + * mxs_dma_read_semaphore - Read a DMA channel's hardware semaphore. + * + * As used by the MXS platform's DMA software, the DMA channel's hardware + * semaphore reflects the number of DMA commands the hardware will process, but + * has not yet finished. This is a volatile value read directly from hardware, + * so it must be be viewed as immediately stale. + * + * If the channel is not marked busy, or has finished processing all its + * commands, this value should be zero. + * + * See mxs_dma_append() for details on how DMA command blocks must be configured + * to maintain the expected behavior of the semaphore's value. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern int mxs_dma_read_semaphore(int channel); + +/** + * mxs_dma_irq_is_pending - Check if a DMA interrupt is pending. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern int mxs_dma_irq_is_pending(int channel); + +/** + * mxs_dma_enable_irq - Enable or disable DMA interrupt. + * + * This function enables the given DMA channel to interrupt the CPU. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @en: True if the interrupt for this channel should be enabled. False + * otherwise. + */ +extern void mxs_dma_enable_irq(int channel, int en); + +/** + * mxs_dma_ack_irq - Clear DMA interrupt. + * + * The software that is using the DMA channel must register to receive its + * interrupts and, when they arrive, must call this function to clear them. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_ack_irq(int channel); + +/** + * mxs_dma_set_target - Set the target for a DMA channel. + * + * This function is NOT used on the i.MX28. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @target: Indicates the target for the channel. + */ +extern void mxs_dma_set_target(int channel, int target); + +/* mxs dma utility functions */ +extern struct mxs_dma_desc *mxs_dma_alloc_desc(void); +extern void mxs_dma_free_desc(struct mxs_dma_desc *); + +/** + * mxs_dma_cmd_address - Return the address of the command within a descriptor. + * + * @desc: The DMA descriptor of interest. + */ +static inline unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc) +{ + return desc->address += offsetof(struct mxs_dma_desc, cmd); +} + +/** + * mxs_dma_desc_pending - Check if descriptor is on a channel's active list. + * + * This function returns the state of a descriptor's "ready" flag. This flag is + * usually set only if the descriptor appears on a channel's active list. The + * descriptor may or may not have already been processed by the hardware. + * + * The "ready" flag is set when the descriptor is submitted to a channel by a + * call to mxs_dma_append() or mxs_dma_append_list(). The "ready" flag is + * cleared when a processed descriptor is moved off the active list by a call + * to mxs_dma_cooked(). The "ready" flag is NOT cleared if the descriptor is + * aborted by a call to mxs_dma_disable(). + * + * @desc: The DMA descriptor of interest. + */ +static inline int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc) +{ + return pdesc->flags & MXS_DMA_DESC_READY; +} + +/** + * mxs_dma_desc_append - Add a DMA descriptor to a channel. + * + * If the descriptor list for this channel is not empty, this function sets the + * CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA command so + * it will chain to the new descriptor's command. + * + * Then, this function marks the new descriptor as "ready," adds it to the end + * of the active descriptor list, and increments the count of pending + * descriptors. + * + * The MXS platform DMA software imposes some rules on DMA commands to maintain + * important invariants. These rules are NOT checked, but they must be carefully + * applied by software that uses MXS DMA channels. + * + * Invariant: + * The DMA channel's hardware semaphore must reflect the number of DMA + * commands the hardware will process, but has not yet finished. + * + * Explanation: + * A DMA channel begins processing commands when its hardware semaphore is + * written with a value greater than zero, and it stops processing commands + * when the semaphore returns to zero. + * + * When a channel finishes a DMA command, it will decrement its semaphore if + * the DECREMENT_SEMAPHORE bit is set in that command's flags bits. + * + * In principle, it's not necessary for the DECREMENT_SEMAPHORE to be set, + * unless it suits the purposes of the software. For example, one could + * construct a series of five DMA commands, with the DECREMENT_SEMAPHORE + * bit set only in the last one. Then, setting the DMA channel's hardware + * semaphore to one would cause the entire series of five commands to be + * processed. However, this example would violate the invariant given above. + * + * Rule: + * ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the DMA + * channel's hardware semaphore will be decremented EVERY time a command is + * processed. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @pdesc: A pointer to the new descriptor. + */ +extern int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); + +/** + * mxs_dma_desc_add_list - Add a list of DMA descriptors to a channel. + * + * This function marks all the new descriptors as "ready," adds them to the end + * of the active descriptor list, and adds the length of the list to the count + * of pending descriptors. + * + * See mxs_dma_desc_append() for important rules that apply to incoming DMA + * descriptors. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @head: A pointer to the head of the list of DMA descriptors to add. + */ +extern int mxs_dma_desc_add_list(int channel, struct list_head *head); + +/** + * mxs_dma_desc_get_cooked - Retrieve processed DMA descriptors. + * + * This function moves all the descriptors from the DMA channel's "done" list to + * the head of the given list. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @head: A pointer to the head of the list that will receive the + * descriptors on the "done" list. + */ +extern int mxs_dma_get_cooked(int channel, struct list_head *head); + +#endif diff --git a/arch/arm/plat-mxs/include/mach/entry-macro.S b/arch/arm/plat-mxs/include/mach/entry-macro.S new file mode 100644 index 000000000000..353a7b2cc8fd --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/entry-macro.S @@ -0,0 +1,36 @@ +/* + * Low-level IRQ helper macros for Freescale MXS-based + * + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =g_icoll_base + ldr \base, [\base] + ldr \irqnr, [\base, #0x70] + cmp \irqnr, #0x7F + moveqs \irqnr, #0 + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm diff --git a/arch/arm/plat-mxs/include/mach/fsl_usb.h b/arch/arm/plat-mxs/include/mach/fsl_usb.h new file mode 100644 index 000000000000..f88324856fc7 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/fsl_usb.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * USB Host side, platform-specific functionality. + */ + +#include <linux/usb/fsl_xcvr.h> +#include <mach/arc_otg.h> + +/* ehci_arc_hc_driver.flags value */ +#define FSL_PLATFORM_HC_FLAGS (HCD_USB2 | HCD_MEMORY) + +static void fsl_setup_phy(struct ehci_hcd *ehci, + enum fsl_usb2_phy_modes phy_mode, + int port_offset); + +static inline void fsl_platform_usb_setup(struct ehci_hcd *ehci) +{ + struct fsl_usb2_platform_data *pdata; + + pdata = ehci_to_hcd(ehci)->self.controller->platform_data; + fsl_setup_phy(ehci, pdata->phy_mode, 0); +} + +static inline void fsl_platform_set_host_mode(struct usb_hcd *hcd) +{ + unsigned int temp; + struct fsl_usb2_platform_data *pdata; + + pdata = hcd->self.controller->platform_data; + + if (pdata->xcvr_ops && pdata->xcvr_ops->set_host) + pdata->xcvr_ops->set_host(); + + /* set host mode */ + temp = readl(hcd->regs + UOG_USBMODE); + writel(temp | USBMODE_CM_HOST, hcd->regs + UOG_USBMODE); +} + +/* Needed for i2c/serial transceivers */ +static inline void +fsl_platform_set_vbus_power(struct fsl_usb2_platform_data *pdata, int on) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->set_vbus_power) + pdata->xcvr_ops->set_vbus_power(pdata->xcvr_ops, pdata, on); +} + +/* Set USB AHB burst length for host */ +static inline void fsl_platform_set_ahb_burst(struct usb_hcd *hcd) +{ +} + +void fsl_phy_usb_utmi_init(struct fsl_xcvr_ops *this); +void fsl_phy_usb_utmi_uninit(struct fsl_xcvr_ops *this); +void fsl_phy_set_power(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, int on); + diff --git a/arch/arm/plat-mxs/include/mach/fsl_usb_gadget.h b/arch/arm/plat-mxs/include/mach/fsl_usb_gadget.h new file mode 100644 index 000000000000..767b344d7e95 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/fsl_usb_gadget.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * USB Gadget side, platform-specific functionality. + */ + +#include <linux/usb/fsl_xcvr.h> + +/* Needed for i2c/serial transceivers */ +static inline void +fsl_platform_set_device_mode(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->set_device) + pdata->xcvr_ops->set_device(); +} + +static inline void +fsl_platform_pullup_enable(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->pullup) + pdata->xcvr_ops->pullup(1); +} + +static inline void +fsl_platform_pullup_disable(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->pullup) + pdata->xcvr_ops->pullup(0); +} diff --git a/arch/arm/plat-mxs/include/mach/gpio.h b/arch/arm/plat-mxs/include/mach/gpio.h new file mode 100644 index 000000000000..7b634149ec23 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/gpio.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include <mach/hardware.h> +#include <asm-generic/gpio.h> + +#define GPIO_ID_NAME "gpio" +/* use gpiolib dispatchers */ +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq +#define irq_to_gpio(irq) ((irq) - MXS_GPIO_IRQ_START) + +struct mxs_gpio_port; +struct mxs_gpio_chip { + int (*set_dir) (struct mxs_gpio_port *, int, unsigned int); + int (*get) (struct mxs_gpio_port *, int); + void (*set) (struct mxs_gpio_port *, int, int); + unsigned int (*get_irq_stat) (struct mxs_gpio_port *); + int (*set_irq_type) (struct mxs_gpio_port *, int, unsigned int); + void (*unmask_irq) (struct mxs_gpio_port *, int); + void (*mask_irq) (struct mxs_gpio_port *, int); + void (*ack_irq) (struct mxs_gpio_port *, int); +}; + +struct mxs_gpio_port { + int id; + int irq; + int child_irq; + struct mxs_gpio_chip *chip; + struct gpio_chip port; +}; + +extern int mxs_add_gpio_port(struct mxs_gpio_port *port); + +static inline void +mxs_set_gpio_chip(struct mxs_gpio_port *port, struct mxs_gpio_chip *chip) +{ + if (port && chip) + port->chip = chip; +} + +#endif /* __ASM_ARCH_GPIO_H__ */ diff --git a/arch/arm/plat-mxs/include/mach/hardware.h b/arch/arm/plat-mxs/include/mach/hardware.h new file mode 100644 index 000000000000..c7dd8fe1d31b --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/hardware.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_HARDWARE_H +#define __ASM_ARM_ARCH_HARDWARE_H + +#ifdef CONFIG_ARCH_MX28 +# include <mach/mx28.h> +# define cpu_is_mx28() 1 +# else +# define cpu_is_mx28() 0 +#endif + +#ifdef CONFIG_ARCH_MX23 +# include <mach/mx23.h> +# define cpu_is_mx23() 1 +# else +# define cpu_is_mx23() 0 +#endif + +#ifndef MXS_EXTEND_IRQS +#define MXS_EXTEND_IRQS 0 +#endif + +#ifndef MXS_ARCH_NR_GPIOS +#define MXS_ARCH_NR_GPIOS 160 +#endif + +#ifndef MXS_EXTEND_NR_GPIOS +#define MXS_EXTEND_NR_GPIOS 0 +#endif + +#define ARCH_NR_GPIOS (MXS_ARCH_NR_GPIOS + MXS_EXTEND_NR_GPIOS) + +#define MXS_GPIO_IRQ_START ARCH_NR_IRQS +#define MXS_EXTEND_IRQ_START (ARCH_NR_IRQS + ARCH_NR_GPIOS) + +#endif /* __ASM_ARM_ARCH_HARDWARE_H */ diff --git a/arch/arm/plat-mxs/include/mach/io.h b/arch/arm/plat-mxs/include/mach/io.h new file mode 100644 index 000000000000..7dff55ef7f12 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/io.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) +#define __mem_isa(a) (a) + +#define SET_REGISTER 0x4 +#define CLR_REGISTER 0x8 +#define TOG_REGISTER 0xC + +struct mxs_io_bank { + unsigned int raw; + unsigned int set; + unsigned int clr; + unsigned int tog; +}; +#endif diff --git a/arch/arm/plat-mxs/include/mach/irqs.h b/arch/arm/plat-mxs/include/mach/irqs.h new file mode 100644 index 000000000000..62165e12a60c --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/irqs.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_IRQS_H__ +#define __ASM_ARCH_IRQS_H__ + +#include <mach/hardware.h> + +#define NR_IRQS (ARCH_NR_IRQS + ARCH_NR_GPIOS + MXS_EXTEND_IRQS) + +#ifndef __ASSEMBLY__ +struct irq_ic_info { + unsigned int id_val; + unsigned int id_mask; + const char *name; + unsigned int base; +}; + +#define __irq_ic_info_attr __attribute__((__section__(".irq_ic_info.array"))) + +extern struct irq_ic_info *current_irq_ic_info; + +void mxs_set_irq_fiq(unsigned int irq, unsigned int type); +void mxs_enable_fiq_functionality(int enable); + +#endif + +#endif /* __ASM_ARCH_SYSTEM_H__ */ diff --git a/arch/arm/plat-mxs/include/mach/lradc.h b/arch/arm/plat-mxs/include/mach/lradc.h new file mode 100644 index 000000000000..c2c0a7deb0b4 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/lradc.h @@ -0,0 +1,61 @@ +/* + * Freescale STMP37XX/STMP378X LRADC helper interface + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_PLAT_LRADC_H +#define __ASM_PLAT_LRADC_H + +int hw_lradc_use_channel(int); +int hw_lradc_unuse_channel(int); +extern u32 hw_lradc_vddio(void); +void hw_lradc_set_delay_trigger_kick(int trigger, int value); +void hw_lradc_configure_channel(int channel, int enable_div2, + int enable_acc, int samples); +int hw_lradc_present(int channel); +int hw_lradc_init_ladder(int channel, int trigger, unsigned sampling); +int hw_lradc_stop_ladder(int channel, int trigger); +void hw_lradc_set_delay_trigger(int trigger, u32 trigger_lradc, + u32 delay_triggers, u32 loops, u32 delays); +void hw_lradc_clear_delay_trigger(int trigger, u32 trigger_lradc, + u32 delay_triggers); + + +#define LRADC_CH0 0 +#define LRADC_CH1 1 +#define LRADC_CH2 2 +#define LRADC_CH3 3 +#define LRADC_CH4 4 +#define LRADC_CH5 5 +#define LRADC_CH6 6 +#define LRADC_CH7 7 +#define LRADC_TOUCH_X_PLUS LRADC_CH2 +#define LRADC_TOUCH_Y_PLUS LRADC_CH3 +#define LRADC_TOUCH_X_MINUS LRADC_CH4 +#define LRADC_TOUCH_Y_MINUS LRADC_CH5 +#define VDDIO_VOLTAGE_CH LRADC_CH6 +#define BATTERY_VOLTAGE_CH LRADC_CH7 + +#define LRADC_CLOCK_6MHZ 0 +#define LRADC_CLOCK_4MHZ 1 +#define LRADC_CLOCK_3MHZ 2 +#define LRADC_CLOCK_2MHZ 3 + +#define LRADC_DELAY_TRIGGER_BUTTON 0 +#define LRADC_DELAY_TRIGGER_BATTERY 1 +#define LRADC_DELAY_TRIGGER_TOUCHSCREEN 2 +#define LRADC_DELAY_TRIGGER_DIE 3 + +#endif /* __ASM_PLAT_LRADC_H */ diff --git a/arch/arm/plat-mxs/include/mach/memory.h b/arch/arm/plat-mxs/include/mach/memory.h new file mode 100644 index 000000000000..051b1608cca4 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/memory.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#include <asm/page.h> +#include <asm/sizes.h> + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET UL(0x40000000) + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_DMA_ZONE_SIZE +#define MXS_DMA_ZONE_SIZE ((CONFIG_DMA_ZONE_SIZE * SZ_1M) >> PAGE_SHIFT) +#else +#define MXS_DMA_ZONE_SIZE ((12 * SZ_1M) >> PAGE_SHIFT) +#endif + +static inline void __arch_adjust_zones(int node, unsigned long *zone_size, + unsigned long *zhole_size) +{ + if (node != 0) + return; + /* Create separate zone to reserve memory for DMA */ + zone_size[1] = zone_size[0] - MXS_DMA_ZONE_SIZE; + zone_size[0] = MXS_DMA_ZONE_SIZE; + zhole_size[1] = zhole_size[0]; + zhole_size[0] = 0; +} + +#define arch_adjust_zones(node, size, holes) \ + __arch_adjust_zones(node, size, holes) + +#endif + +#define ISA_DMA_THRESHOLD (0x0003ffffULL) + +#define CONSISTENT_DMA_SIZE SZ_32M + +#endif diff --git a/arch/arm/plat-mxs/include/mach/pinctrl.h b/arch/arm/plat-mxs/include/mach/pinctrl.h new file mode 100644 index 000000000000..6e02149f5ca6 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/pinctrl.h @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_PINCTRL_H +#define __ASM_ARM_ARCH_PINCTRL_H + +#include <linux/types.h> +#include <linux/gpio.h> + +#define PINS_PER_BANK 32 +#define GPIO_TO_PINS(gpio) ((gpio) % 32) +#define GPIO_TO_BANK(gpio) ((gpio) / 32) + +#define MXS_PIN_TO_GPIO(p) (((p) & MXS_PIN_PINID_MAX) |\ + ((((p) >> MXS_PIN_BANK_BIT) &\ + MXS_PIN_BANK_MAX) * PINS_PER_BANK)) + +#define MXS_PIN_BANK_BIT 24 +#define MXS_PIN_BANK_MAX (0x7FFFFFFF >> (MXS_PIN_BANK_BIT - 1)) +#define MXS_PIN_PINID_MAX ((1 << MXS_PIN_BANK_BIT) - 1) +#define MXS_PIN_TO_BANK(p) (((p) >> MXS_PIN_BANK_BIT) & MXS_PIN_BANK_MAX) +#define MXS_PIN_TO_PINID(p) ((p) & MXS_PIN_PINID_MAX) + +#define MXS_PIN_ENCODE(b, p) \ + ((((b) & MXS_PIN_BANK_MAX) << MXS_PIN_BANK_BIT) |\ + ((p) & MXS_PIN_PINID_MAX)) + +#define MXS_GPIO_MASK 0x7FFFFFFF +#define MXS_NON_GPIO 0x80000000 +/* + * Each pin may be routed up to four different HW interfaces + * including GPIO + */ +enum pin_fun { + PIN_FUN1 = 0, + PIN_FUN2, + PIN_FUN3, + PIN_GPIO, +}; + +/* + * Each pin may have different output drive strength in range from + * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths. + */ +enum pad_strength { + PAD_4MA = 0, + PAD_8MA, + PAD_12MA, + PAD_RESV, + PAD_CLEAR = PAD_RESV, +}; + +/* + * Each pin can be programmed for 1.8V or 3.3V + */ +enum pad_voltage { + PAD_1_8V = 0, + PAD_3_3V, +}; + +/** + * struct pin_desc - Describes the configuration of a pin. + * + * @name: A human-readable name that identifies the pin. + * @id: A number that identifies the pin (use a macro from a chip- + * specific header file -- e.g., "PINID_PWM0"). + * @fun: The function for which to configure this pin. + * @strength: The drive strength for this pin. Note that this field should be + * ignored and the driver hardware should *not* be configured if the + * "drive" field is not set. + * @voltage: The voltage rail for this pin. Note that this field should be + * ignored and the driver hardware should *not* be configured if the + * "drive" field is not set. + * @pullup: If set, indicates whether the pullup is enabled. Note that this + * field should be ignored and the pullup should *not* be configured + * if the "pull" field is not set. + * @drive: If set, indicates that the driver hardware for this pin should be + * configured. This field does *not* indicate *how* the driver + * hardware should be configured -- only whether or not it should + * be. See the "strength" and "voltage" fields for information about + * how to configure the driver hardware. + * @pull: If set, indicates that the pullup for this pin should be + * configured. This field does *not* indicate *how* the pullup + * should be configured -- only whether or not it should be. See the + * "pullup" field for information about how to configure the pullup. + * @input: For GPIO pins only, this indicates whether the pin is an input. + * @data: The data field is used when the pin is configured to GPIO output + * mode. When data is 0, the pin's output will be 0. + */ +struct pin_desc { + char *name; + unsigned int id; + enum pin_fun fun; + enum pad_strength strength; + enum pad_voltage voltage; + unsigned pullup:1; + unsigned drive:1; + unsigned pull:1; + unsigned output:1; + unsigned data:1; +}; + +struct pin_bank { + const char *label[sizeof(long) * 8]; + unsigned long id; + struct pinctrl_chip *chip; + unsigned long bitmap; + unsigned long gpio_port; +}; + +struct pinctrl_chip { + char *name; + unsigned int nouse; + unsigned int bank_size; + struct pin_bank *banks; + /* OPS */ + int (*pin2id) (struct pinctrl_chip *, unsigned int, unsigned int *); + unsigned int (*get_gpio) (struct pin_bank *, unsigned int); + void (*set_strength) (struct pin_bank *, unsigned int, + enum pad_strength); + void (*set_voltage) (struct pin_bank *, unsigned int, enum pad_voltage); + void (*set_pullup) (struct pin_bank *, unsigned int, int); + void (*set_type) (struct pin_bank *, unsigned int, enum pin_fun); + int (*get_type) (struct pin_bank *, unsigned int); +}; + +extern int __init mxs_set_pinctrl_chip(struct pinctrl_chip *); + +extern unsigned int mxs_pin2gpio(unsigned int); +extern int mxs_request_pin(unsigned int, enum pin_fun, const char *); +extern int mxs_set_type(unsigned int, enum pin_fun, const char *); +extern int mxs_get_type(unsigned int); +extern int mxs_set_strength(unsigned int, enum pad_strength, const char *); +extern int mxs_set_voltage(unsigned int, enum pad_voltage, const char *); +extern int mxs_set_pullup(unsigned int, int, const char *); +extern void mxs_release_pin(unsigned int, const char *); +#endif diff --git a/arch/arm/plat-mxs/include/mach/power.h b/arch/arm/plat-mxs/include/mach/power.h new file mode 100644 index 000000000000..28ee9fa2696d --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/power.h @@ -0,0 +1,64 @@ +/* + * Freescale MXS voltage regulator structure declarations + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __VOLTAGE_H +#define __VOLTAGE_H +#include <linux/completion.h> +#include <linux/regulator/driver.h> + +struct mxs_regulator { + struct regulator_desc regulator; + struct mxs_regulator *parent; + struct mxs_platform_regulator_data *rdata; + struct completion done; + + spinlock_t lock; + wait_queue_head_t wait_q; + struct notifier_block nb; + + int mode; + int cur_voltage; + int cur_current; + int next_current; +}; + + +struct mxs_platform_regulator_data { + char name[80]; + char *parent_name; + int (*reg_register)(struct mxs_regulator *sreg); + int (*set_voltage)(struct mxs_regulator *sreg, int uv); + int (*get_voltage)(struct mxs_regulator *sreg); + int (*set_current)(struct mxs_regulator *sreg, int uA); + int (*get_current)(struct mxs_regulator *sreg); + int (*enable)(struct mxs_regulator *sreg); + int (*disable)(struct mxs_regulator *sreg); + int (*is_enabled)(struct mxs_regulator *sreg); + int (*set_mode)(struct mxs_regulator *sreg, int mode); + int (*get_mode)(struct mxs_regulator *sreg); + int (*get_optimum_mode)(struct mxs_regulator *sreg, + int input_uV, int output_uV, int load_uA); + u32 control_reg; + int min_voltage; + int max_voltage; + int max_current; + struct regulation_constraints *cnstraints; +}; + +int mxs_register_regulator( + struct mxs_regulator *reg_data, int reg, + struct regulator_init_data *initdata); + +#endif /* __VOLTAGE_H */ diff --git a/arch/arm/plat-mxs/include/mach/system.h b/arch/arm/plat-mxs/include/mach/system.h new file mode 100644 index 000000000000..faaa2ff3cf13 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/system.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_SYSTEM_H__ +#define __ASM_ARCH_SYSTEM_H__ + +extern void arch_idle(void); + +void arch_reset(char mode, const char *cmd); +extern void (*machine_arch_reset)(char mode, const char *cmd); +int mxs_reset_block(void __iomem *hwreg, int just_enable); +int get_evk_board_version(void); + +#endif /* __ASM_ARCH_SYSTEM_H__ */ diff --git a/arch/arm/plat-mxs/include/mach/timex.h b/arch/arm/plat-mxs/include/mach/timex.h new file mode 100644 index 000000000000..d622dda141f2 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/timex.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * System time clock is sourced from the 32k clock + */ +#define CLOCK_TICK_RATE 32000 diff --git a/arch/arm/plat-mxs/include/mach/uncompress.h b/arch/arm/plat-mxs/include/mach/uncompress.h new file mode 100644 index 000000000000..fd4e4f845472 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/uncompress.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_PLAT_UNCOMPRESS_H +#define __ASM_PLAT_UNCOMPRESS_H + +#include <mach/hardware.h> + +/* + * Register includes are for when the MMU enabled; we need to define our + * own stuff here for pre-MMU use + */ +#define UART_PORT_BASE DUART_PHYS_ADDR +#define UART(c) (((volatile unsigned *)UART_PORT_BASE)[c]) + +/* + * This does not append a newline + */ +static void putc(char c) +{ + /* Wait for TX fifo empty */ + while ((UART(6) & (1 << 7)) == 0) + continue; + + /* Write byte */ + UART(0) = c; + + /* Wait for last bit to exit the UART */ + while (UART(6) & (1 << 3)) + continue; +} + +#define flush() do { } while (0) +/* + * nothing to do + */ +#define arch_decomp_setup() + +#define arch_decomp_wdog() + +#endif /* __ASM_PLAT_UNCOMPRESS_H */ diff --git a/arch/arm/plat-mxs/include/mach/unique-id.h b/arch/arm/plat-mxs/include/mach/unique-id.h new file mode 100644 index 000000000000..de5e04342ef5 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/unique-id.h @@ -0,0 +1,30 @@ +/* + * Unique ID interface for ID storage providers + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __UNIQUE_ID_H +#define __UNIQUE_ID_H + +struct uid_ops { + ssize_t (*id_show)(void *context, char *page, int ascii); + ssize_t (*id_store)(void *context, const char *page, + size_t count, int ascii); +}; + +struct kobject *uid_provider_init(const char *name, + struct uid_ops *ops, void *context); +void uid_provider_remove(const char *name); +#endif diff --git a/arch/arm/plat-mxs/include/mach/vmalloc.h b/arch/arm/plat-mxs/include/mach/vmalloc.h new file mode 100644 index 000000000000..cc6d5cf3133a --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/vmalloc.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#define VMALLOC_END (0xF0000000) |